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Design for e-beam methodology validated for 65-nm SOC apps, say eBeam Initiative collaborators

27 May 2009 | By Tom Cheyney | News > Lithography

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fujitsu_ebeamD2S, e-Shuttle, and Fujitsu Microelectronics, all steering group members of the eBeam Initiative, say they have validated the design for electron beam (DFEB) methodology for low-volume, 65-nm system-on-chip applications, without sacrificing performance, area, or power.

DFEB combines software and design technologies that enable advanced character projection e-beam direct-write (EbDW) equipment to reduce shot count, thus making EbDW throughput feasible for low-volume designs.

The final estimated shot count for the test chip using DFEB represented a more than 10X reduction over conventional EbDW technologies, while also meeting the required performance, power, and area goals.

The collaborative effort included D2S and Fujitsu Microelectronics working on the design, while e-Shuttle manufactured the test chip to confirm the DFEB technology for the 65-nm node. D2S designed the DFEB library overlay with Fujitsu Microelectronics, and also partnered closely with e-Shuttle and Advantest on the stencil mask used in the fab's EbDW machine.

Prototyping is a target application for DFEB, and with e-Shuttle's experience in these services, the company was able to validate the applicability of DFEB for prototyping.

"With this test chip, we now have tangible results that DFEB is enabling us to meet the necessary shot count requirements without sacrificing the quality of design results. DFEB makes maskless prototypes practical now," according to Yoji Hino, corporate executive VP of Fujitsu Microelectronics and member of the initiative's steering group.

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