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CEA-Leti research achieves CMOS compatibility with synthetic silicon nanowires
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Micro- and nanotechnology research and development institute CEA-Leti has made strides in its silicon nanowire synthesis. Researchers have found that there exists a compatibility between CMOS technology and bottom-up growth of nanowires, and that synthesis of silicon nanowire can be carried out at temperatures as low as 400°C by using a copper-based catalyst and an unconventional preparation method.
CMOS is the most commonly used technology in silicon IC manufacturing. Achieving the growth of silicon nanowires with a CMOS-compatible catalyst and at CMOS-compatible temperatures will cater for a realm of new products on the market. While research is ongoing, this discovery opens the door for the inclusion of new non-digital functions such as sensors and advanced photovoltaic architectures in chip manufacturing.
The findings were published in the recent issue of Nature Nanotechnology, within which the Leti researchers explained their new approach to nanowire growth. Questioning the assumption that oxidized metals are not suitable for nanowire synthesis, Leti decided instead to oxidize the copper catalyst, using the high chemical activity of this oxide to reduce synthesis temperature of the nanowires.
The published paper is available here.