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Blaze DFM has signed an exclusive agreement with TSMC that allows the foundry to offer customers Blaze’s Power Trim Service, which identifies paths in the design that have sufficient timing ‘slack’ so that transistors can be turned down to save power consumption without reducing the performance of the chip.  TSMC is using the service, currently available to a limited number of selected customers on its 90nm, 80nm, 65nm, 55nm, and 45nm process nodes. However, two of the top five fabless companies have already fabricated chips with this process option at TSMC and others are being added selectively during a phased rollout of the technology.

"Power leakage has long been an issue for IC designs, especially in the smaller geometries," said Fu-Chieh Hsu, Vice President of Design & Technology Platform at TSMC. "With the Blaze DFM technology, we now have a tool that discovers areas for optimization that was not previously possible. This means we can provide customers with the ability to minimize power leakage problems, thereby saving their time and money to meet the market demand."

"TSMC has produced exciting results for our mutual customers during the silicon validation process," said Jacob Jacobsson, CEO of Blaze DFM, Inc. "Now customers can have easy access to our patented technology directly from TSMC as part of TSMC's Power Trim Service. This is just the first of several technologies that Blaze intends to bring to the market by leveraging our unique position at the design to manufacturing handoff and our partnership with TSMC."

Customers will not be required to separately purchase or license any software from Blaze.