Online information source for semiconductor professionals

ASM offers single metal gate stack for 32nm logic processes

19 May 2008 | By Mark Osborne | News > Wafer Processing

Popular articles

Voltaix names Peter Smith as CEO - 09 November 2011

Sematech Litho Forum: Sematech mulling multi-beam mask writer effort - 12 May 2010

TSMC hosts 2008 Green Forum on ‘green’ factories - 31 October 2008

Oberai discusses Magma’s move into solar PV yield management space - 29 August 2008

TSMC honors suppliers at annual Supply Chain Management Forum - 03 December 2008

ASMASM America, a subsidiary of ASM International, has developed an atomic layer deposition (ALD) process implementing lanthanum oxide (LaOx) and aluminum oxide (AlOx) high-k cap layers that enable 32nm generation high-k metal gate stacks using a single metal, instead of the two different metals first implemented with 45nm logic devices.

“Solving the integration challenges for high-k metal gates is a top priority for most of our customers,” explained Glen Wilk, Product Manager for transistor products at ASM. “This new process greatly simplifies the high-k metal gate integration and allows us to support gate first, as well as gate last process flows.  ASM now offers ALD processes for the high-k dielectric, cap layer, and metal gate.”

According to ASM, two different metals are needed to create the proper electrical characteristics of both sides (p and n) of the transistor switch, when not using a capping layer.  The use of an ultra-thin cap film between the hafnium-based gate dielectric and the metal gate, atomic level charges will affect the interaction between the dielectric and the metal.  

The proper metal film performance can be tuned by varying the cap film’s thickness in a range less than 1nm. ASM used its ‘Pulsar’ process module to deposit the films.

Related jobs

No related jobs found, sorry!

Related articles

front end surface preparation challenges and solutions for 65- and 45-nm technology nodes - 01 December 2005

IMEC reduces high-k/metal gate process steps from 15 to 9 - 17 June 2008

Advanced gate electrodes for future generation CMOS - 01 December 2004

Panasonic and Renesas use HKMG with ultra-low-k for 32nm SoC devices - 09 October 2008

Toshiba illustrates cost-effective 32nm CMOS platform technology - 18 December 2008

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: