EV Group has entered into a joint development agreement with Applied Materials that will see the companies collaborate on wafer bonding processes for the manufacture of through-silicon vias in three-dimensional integrated circuit (3D IC) packaging applications. The companies will work together as members of the EMC-3D Semiconductor 3D Equipment and Materials Consortium.
TSV technology is finding its niche as consumers seek out smaller and more compact electronic devices. While conventional ICs use 750-μm-thick wafers, 3D ICs use much thinner wafers - about 100μm or less – and so require different processing techniques to avoid loss of structural and edge integrity in high-temperature, high-stress processes such as metallization.
EV Group and Applied Materials will work to remedy these obstacles by bonding temporary carrier wafers to device wafers prior to thinning. These carriers will provide structural support to the thin device wafers in the process steps, and will then be removed. The companies will also investigate substrate stability in using silicon and glass carrier wafers.
It is hoped that the companies can determine the baseline processes and recommendations for carrier-mounted wafers in relation to the various process steps covered by each company’s respective expertise. The results of the research will be made available to EMC-3D member companies.
“This is a continuation of our strategy to form alliances with leading equipment suppliers such as EVG to deliver fully-characterized TSV process flows to accelerate customers’ time to market,” said Hans Stork, group vice president and chief technology officer of Applied’s Silicon Systems Group. “We look forward to working with EVG at Applied’s Maydan Technology Center in advancing this disruptive technology and expediting the adoption of TSVs for mainstream manufacturing.”