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AMD and IBM have said they have successfully produced a working test chip utilizing “full-field” EUV lithography for the critical first layer - instead of ‘narrow field’ (R&D sample applications) - in the fabrication process across an entire 22mm x 33mm AMD 45nm node test chip.

“This important demonstration of EUV lithography’s potential to be used in semiconductor manufacturing in the coming years is encouraging to all of us in the industry that benefit from chip feature sizes shrinking over time,” said Dr. Bruno La Fontaine of AMD. “Although there is still a lot of work to be done before the industry can use EUV lithography in high volume production, AMD has shown it can be integrated successfully in a semiconductor fabrication flow to produce the first layer of metal interconnects across a full chip.”

The AMD test chip first went through processing at AMD’s Fab 36 in Dresden then shipped for imaging using the EUV Alpha tool from ASML at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York.

The next step will be to apply EUV to all critical layers including metal interconnects to demonstrate that a complete working microprocessor can be fabricated using EUV lithography.