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Accretech adds name to SEMATECH‚??s 3D Interconnect Program

27 February 2008 | By Síle Mc Mahon | News > Wafer Processing

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SEMATECHAccretech Tokyo Seimitsu has become an associate member in SEMATECH’s 3D Interconnect Program located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. Launched two years ago, the 3D program, which includes research into through-silicon vias (TSVs) as interconnects, is working to enable high-volume manufacturing of 3D chips by its members. 

“Being able to thin wafers uniformly with minimal damage and then handle the thinned wafers during subsequent processing are critical requirements for 3D processing,” said Sitaram Arkalgud, SEMATECH’s 3D program director. “Accretech is well known and respected throughout the semiconductor community for its expertise in the area of wafer thinning, handling and dicing, and their participation in SEMATECH’s 3D program will be very valuable.  We share the belief that 3D integration will be a key driver of chip performance and functionality, and working together we will accelerate progress toward industry-wide implementation.”

Should the development work prove successful, then 3D interconnects will eventually link CMOS chips with MEMS, NEMS and bio-chips amongst ultra small form factor CMOS device staking.

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