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SEZ notes demise of wet benches at the 65nm node

04 November 2005 | Wafer Processing
SEZ Group's, recently promoted COO, Kurt Lackenbucher, noted during an analyst conference call to discuss the company's 3Q05 results that it was seeing a concerted shift away from wet bench processes to single wafer platforms as chip manufacturers prepared to start 65nm production. Read more >>

IBM & AMD aim alliance at the 22nm frontier

01 November 2005 | Wafer Processing
IBM and AMD have expanded and extended their semiconductor R&D alliance to include the 32nm and 22nm technology nodes. In an effort to develop the required processes for volume manufacturing at these nodes the alliance will be expanded to include more fundamental research into new materials that are expected to be required. According to IBM, this is the first time a technology alliance partner has teamed with IBM in such a way. Read more >>

Tool Order: Major Japanese Chipmaker buys a VIISta HC ion-implanter

28 October 2005 | Wafer Processing
A major Japanese IC manufacturer has placed an order for a single wafer high current ion-implanter from Varian Semiconductor Equipment Associates, Inc. The tool, a VIISta 300mm wafer system is the first tool order the Japanese company has placed with Varian Semiconductor and is to be used for 65nm processing duties. "For the first time, this customer placed an order for Varian Semiconductor's VIISta HC expanding the Company's considerable lead in single wafer high current," said Gary Dickerson, chief executive officer of  Varian Semiconductor. Dickerson continued, "As Japan continues to transition from batch to single wafer, Varian Semiconductor's VIISta single wafer high current tools are becoming the tool of choice based on key architectural advantages. Read more >>

Tool Order: Axcelis receives first order for Optima HD ion implanter

27 October 2005 | Wafer Processing
Axcelis Technologies, Inc. commented during its third quarter financial analyst conference call that the company has received the first order for its newly launched high dose implanter, based on the Optima platform. The multiple tool order should be shipped in the 4Q05, though the company declined to provide further information. Read more >>

Tool orders: Peter Wolters selects ADE‚??s wafer mapping & edge roll-off tool

26 October 2005 | Wafer Processing
Peter Wolters AG, a subsidiary of Novellus Systems Inc, has purchased ADE's "WaferSight" a high resolution (35nm) wafer geometry system for its R&D laboratory in Germany. Read more >>

Tool Orders: Japanese 300mm fab orders Therma-Wave‚??s Opti-Probe systems

19 October 2005 | Wafer Processing
A Japanese 300mm logic fab has placed a multi-million dollar, multi-tool order for Therma-Wave, Inc's Opti-Probe 7341XP thin-film and critical dimension metrology systems. The tools will be used to support front end as well as back end 300mm logic device manufacturing processes at the 90nm node as part of a transition to copper based production. Read more >>

UMC makes Axcelis stripper ‚??tool of record‚?Ě

17 October 2005 | Wafer Processing
Taiwan foundry UMC has put in a follow-on order for Axcelis Technologies' RadiantStrip 320Lk photoresist dry strip and cleaning system. The RadiantStrip 320Lk system has become UMC's "process tool of record". The system will ship to UMC's Fab 12A in Tainan, Taiwan, by the end of 2005. Read more >>

Freescale has said it will enter into 65nm node device prototyping in November

11 October 2005 | Wafer Processing
Freescale Semiconductor plans to enter into 65nm IC prototyping in November of this year. Work will be carried out at the Crolles2 joint development facility with STM and Philips in Crolles, France. "We have addressed many of the industry's widely reported challenges with 90-nm and are applying our expertise to the next generations of technology," said Freescale's Chief Technology Officer Dr. Claudine Simson. "Our achievements at 90-nm over the past year set the stage for successful 65-nm prototyping, which we will begin in November." Read more >>

Oki Electric reveals fully depleted SOI process with reverse polarity

06 October 2005 | Wafer Processing
Oki Electric Industry Co., Ltd has presented details of its fully depleted SOI process that it claims reduces standby leakage current by over 90 percent yet retains performance figures of its previous SOI devices. This was achieved by using a transistor that had a non-doped body and non-overlap type SOI structure. The device was revealed during 2005 SOI Conference in Honolulu, Hawaii. Read more >>

TSMC starts customer 65nm prototype wafer shuttle service

05 October 2005 | Wafer Processing
Taiwan Semiconductor Manufacturing Company has completed the first of three CyberShuttle prototype production runs for its 65nm process technology. According to the Taiwanese foundry, five customers' designs and multiple 3rd party IP designs are on the first shuttle. Fabless companies taking part included Altera and Broadcom. On the IDM side, Freescale has also taken part. TSMC also reiterated that the wafer shuttle service contained both a low power process and a high performance process. Beginning in 2006, TSMC will launch additional 65nm shuttles every other month, enabling customers and EDA, IP and library suppliers to prototype and qualify 65nm designs. Read more >>