C. S. Park, G. Bersuker, S. C. Song, P. Kirsch & B. H. Lee, SEMATECH, Austin, Texas; R. Jammy, IBM assignee to SEMATECH

ABSTRACT

This paper describes recent progress in high-k/metal gate stacks required for MOSFET scaling to the 32nm technology node. Band-edge metals for n- and p-MOSFETs have been developed through effective work function (WF) tuning, achieved by optimized doping of the high-k gate stacks. The mechanism of the EWF tuning is the dipole formation at the interface of the high-k dielectric and SiO₂ interfacial layer. Possible solutions to the flatband voltage (V_fb) roll-off issue were obtained, an issue that presents the most significant challenge to achieving low pMOSFET threshold voltage (|V_t|) at low EOTs. The gate-first high-k/metal gated n- and pMOSFETs with low |V_t| and low EOT suitable for 32nm technology node applications have been successfully demonstrated.

Paul Kirsch, S.C.Song, & Prashant Majhi, SEMATECH, & Raj Jammy, IBM assignee to SEMATECH

ABSTRACT

Historically, both logic and memory have been front-end process technology drivers.  For example, logic development resulted in shallow trench isolation eliminating “bird’s beak” isolation oxide. Ion implantation increased doping densities needed for high mobility n-channel transistors.  More recently, embedded SiGe, dual stress nitride, Hf-based high-k and metal gates have been logic performance drivers. On the other hand, memory development has spawned plasma doping, nitrided oxides, Al-based high-k and borderless contacts, as well as pushed lithography critical dimension. Motivation for memory development work is multi-fold. First, memory revenues grow faster than logic revenues. Second, the growth potential of memory materials and processes in embedded applications holds tremendous promise to improve system level performance. Finally, many new materials are emerging to address memory-scaling challenges but screening these many options is difficult.  Building on extensive knowledge of gate dielectric and metal gate materials gained through several years of experience, SEMATECH is pursuing the challenge of materials development for DRAMs, Flash, PRAM, and ReRAM as described below. SEMATECH has successfully provided solutions to the semiconductor industry and this deep knowledge accelerates memory progress. 

By Don Baskin and Paul Scheibmeir, ATDF, Texas, USA

ABSTRACT

Atomic layer deposition (ALD) has become a leading technology candidate for enabling the semiconductor industry to fabricate devices below 90nm and forge into the realm of nanotechnology.  One of the most effective precursors for ALD is trimethylaluminum (TMAl), a pyrophoric liquid that ignites upon contact with air and reacts violently with water or atmospheric moisture.  Because of its reactivity, TMAl requires strict safety protocols for handling, containment, and use.  Becoming familiar with andadopting these procedures may require a steep learning curve and rapid assimilation of new safety regiments.  Such was the experience of ATDF, the global R&D foundry based in Austin, TX.

By Mark R. Litchy, Donald C. Grant, CT Associates, Inc., USA and Reto Schoeb, Levitronix GmbH, Switzerland

ABSTRACT

Delivery systems used to supply slurry to CMP planarization tools can damage slurry.  In this experiment, four slurries were circulated in a simulated slurry delivery loop at a fixed flow rate and pressure using a variety of pumps (bellows, diaphragm, and magnetically levitated centrifugal) to determine the effect of circulation on the slurry health.  During each test, a number of slurry health parameters were monitored including the size distribution of the particles in the slurry. Most slurry health parameters were unaffected during the tests.  However, significant changes in the large particle tail (particles ≥ 0.5μm) of the slurry particle size distributions (PSD) were observed.  Both the pump and slurry type played important roles in the magnitude of the change.  In some slurries, large increases in the large particle concentrations were observed during circulation with diaphragm and bellows pumps, while in other slurries increases were not observed.  With the magnetically levitated centrifugal pumps, minimal changes were observed, regardless of the type of slurry tested.

Robert L. Rhoades, Entrepix, Inc., Arizona, USA, & Gautam Banerjee, Air Products and Chemicals, Inc., Arizona, USA

ABSTRACT

Advanced semiconductor devices have evolved over recent years through a series of steps that included the introduction of both copper metal and low-k dielectric materials for the interconnect module. As designs continue to push toward faster speeds and smaller linewidths (65, 45, 32 and 22nm), the dielectric constant (k) required at each successive technology node is projected to continue dropping toward effective k-values of 2.5 or below. The new materials required to reach these values are generally referred to as ultra low-k, or ULK, dielectrics. Developing such ULK materials is an incredible challenge, but several candidate materials are now available. However, integrating them successfully into a reliable CMOS device manufacturing flow is proving to be extremely difficult, especially with regard to the CMP process module.  

C.P. Jones, A.M. Pierce, B.R. Roberts, BOC Edwards, USA

ABSTRACT

Electrochemically regenerated ion exchange (ERIX™) concentrates chemical waste and recovers water for reuse.  ERIX incorporates proven electro-deionization (EDI) technology, ion exchange and electro-dialysis in a single cell.  EDI and ion exchange are used commercially to produce ultra-pure water.  In EDI cells, the mixed-bed ion exchange deionizes the solution as it passes through.  The electrodialytic components move the ions from the resin to a concentrate stream, thereby achieving a continuous ion exchange process without the need for periodic regeneration of the cell or addition of regenerant chamicals.  ERIX can be used for the removal of both cations and anions. 

Robert Preisser, Atotech Deutschland, Berlin, Germany

ABSTRACT

The introduction of copper metallization into semiconductor manufacturing has been a significant step in process technology and device scaling. However, the wet electro-deposition technology used suffers from a number of drawbacks. Impurities deposited on the copper anode from organic additives in the electrolyte solution can subsequently be released and deposited on the wafer, leading to killer-defect particles. Also, gas bubbles from the electrolytic decomposition of water can be trapped in the deposited metal, leading to further process issues. 

Josep Arnó, R&D Director, ATMI Inc., & Craig Printy, National Semiconductor, USA

ABSTRACT

Under certain circumstances, the manufacture of electronic devices requires the use of dilute gases. These materials are typically supplied in premixed high-pressure cylinders containing the active gas in a dilute form. The pressures and delivery flow rates of these precursors are accurately controlled through sophisticated delivery systems that include mass flow controllers, pressure regulators, and transducers. However, typical delivery systems do not integrate equipment that measures the accuracy and real-time stability of the gas blend composition. Such chemical analyzers may be especially important to monitor the concentration of mixtures during doping applications where precise dosing is critical. 

J. Connelly & W. Curcie, Infineon Technologies, Richmond, Virginia, USA

ABSTRACT

In high-volume semiconductor factories (Fabs), the use of tote supply for chemicals and slurries can significantly reduce operating costs. In cases where systems were not originally designed to accommodate totes, transitioning to a tote supply may require custom engineering and logistics solutions. This article relates the experiences of one factory in transitioning several systems from drum to tote supply. These efforts saved over $340,000 annually. 

Bill Reith, Senior Supplier Quality Engineer, Freescale Semiconductor, Scotland

ABSTRACT

Developing and releasing a material specification is only a starting point from which subsequent and ongoing improvements ensue. In order to optimize the performance of any material it is important to verify, using support data, the critical requirements for the product in the device or process application. Armed with knowledge of the critical parameters, you can compare objectively the performance of different materials from different suppliers.  

Christophe Maleville, Christelle Michau, Daniel Delprat, Soitec SA, Crolles, France, & Arun Srivatsa, KLA-Tencor, San Jose, CA, USA

ABSTRACT

With shrinking device geometries, we are now witnessing an increased adoption of silicon-on-insulator (SOI) substrates in mainstream semiconductor fabrication (replacing bare silicon (Si) and epi substrates) to realize the advantages of SOI for improved device performance. The superficial Si thickness in SOI structures is also shrinking with each node as semiconductor manufacturers migrate from partially depleted SOI (PD-SOI) to fully depleted SOI (FD-SOI). 

P.R. Chidambaram, Texas Instruments, Richardson, TX, USA

ABSTRACT

In the last year most semiconductor manufacturers have announced the use of some form of strain enhancement in their production technology [1-4]. Strain is the most popular means of realizing the required node-on-node transistor performance improvements in recent times. This article will review the most popular and manufacturable strained silicon technologies. 

A. Soulet, L. Duquesne, G. Jursich & R. Inman, American Air Liquide, Chicago research Center, IL, USA, A. Misra, Air Liquide Electronics U.S. LP, Dallas, TX, USA, N. Blasco, C. Lachaud, Y. Marot, R. Prunier & M. Vautier, Air Liquide Centre de Recherches Claude Delorme,Jouy-en-Josas, France, & S. Anderson, P. Clancy & M. Havlicek, Air Liquide - Balazs™ Analytical Services, CA, USA

ABSTRACT

Selecting a precursor for gate oxide deposition requires extensive characterization of targeted molecules. In this article, we show how these characterizations help in preventing precursors' degradation, identifying gas-phase species and defining process windows and distribution parameters. 

John Gumpher, Tokyo Electron America, Austin, TX, USA, Narendra Mehta & Wayne Bather, Texas Instruments, Dallas, TX, USA

ABSTRACT

This study examines the effects of hydrogen incorporation and silicon nitride film stress on boron dose retention; and indicate that increased boron retention can be achieved not only by reduction of hydrogen levels in the silicon nitride film, but also by increasing tensile film stress in the silicon nitride over-layer. 

V. Vartanian, B-Y Nguyen, A. Thean, D. Zhang, S. Zollner, T. White, M. Sadaka, B. Goolsby, V. Dhandapani, J. Hildreth, L. McCormick, D. Theodore, Q. Xie, X-D Wang, M. Canonico, M. Kottke, Z. Shi, L. Mathew, M. Zavala, C. Parker, H. Collard, L. Prabhu, R. Rai, S. Murphy, P. Montgomery, S. Kalpat, M. Ramon, V. Adams, J. Jiang, J. Chen, V. Kaushik, M. Sadd, A. Barr, A. Vandooren, D. Pham, V. Kolagunta, M. Orlowski, N. Ramani, S. Vanketesan & J. Mogab, Freescale Semiconductor, Inc., Advanced Products Research and Development Laboratory, Austin, Texas, USA

ABSTRACT

The semiconductor industry has traditionally relied on reducing transistor dimensions such as gate length and gate oxide thickness to improve circuit performance. However, as gate lengths are reduced below 30 nm, new materials, processes, and device structures are required to overcome the fundamental physical limitations of conventional transistor materials and designs. 

Amir Al-Bayati, Lori Washington, Li-Qun Xia, Mihaela Balseanu, Zheng Yuan, Mark Kawaguchi,Faran Nouri & Reza Arghavani, Applied Materials, Inc., USA

ABSTRACT

A key method being used to extend Moore's Law to the 45nm node and beyond is to induce local, uniaxial tensile/compressive strain in the channel of a MOSFET to dramatically boost device performance. Three different families of films are the leading approaches for stress induction. Newly developed silicon nitride (SiN) films with stress varying from -3.0GPa to 1.9GPa can induce stress in the channel when used over a gate stack or engineered into STI processing. Tensile and compressive oxides induce further stress when used in STI or post gate stack processing. Finally, the use of selective epitaxial SiGe deposited in recessed/raised source/drain structures is an alternative method of stress induction. 

Kirklen Henson & Malgorzata Jurczak, IMEC, Leuven, Belgium

ABSTRACT

The introduction of metal gates into CMOS technology faces significant challenges. First, appropriate materials and processes must be identified that give the desired symmetry and magnitude of device threshold voltage. Secondly, a cost-effective integration scheme must be developed for manufacturing. Thirdly, the metal-gate solutions should be scalable to future technologies. Achieving symmetric threshold voltages requires multiple work functions: one for the NMOS and one for the PMOS device. 

Professor Peter Ashburn, Director & Technical Advisor, Innos, Southampton, UK Huda El Mubarek, School of Electronics & Computer Science, Southampton University, UK

ABSTRACT

Boron diffuses relatively quickly in silicon at temperatures typically used for anneals in CMOS and bipolar technologies making it hard to precisely control the location of the doping profiles and very difficult to form very shallow boron-doped junctions. This problem is much worse when anneals are carried out after ion implantation because of transient enhanced diffusion, which is caused by damage introduced during ion implantation, and arises because dopants diffuse with the aid of point defects, interstitials in the case of boron. Transient enhanced diffusion can enhance the diffusion coefficient of boron by as much as an order of magnitude during the short anneals typically used in rapid thermal annealing. 

D.E. Joyce & P.A. Ryan, Bede, Durham, UK, & M.Wormington, Bede, Englewood, CO, USA

ABSTRACT

This article describes the use of modern X-ray diffraction equipment in the field of SiGe assessment. Strain, composition and layer thicknesses can all be measured on production wafers, i.e. nondestructively at high spatial resolution and high accuracy. 

C. M. Osburn, A. Kingon, G. Lucovsky, J. P. Maria, V. Misra & G. Parsons,; North Carolina State University & S. A. Campbell, University of Minnesota, E. Eisenbraun, University of Albany, E. Garfunkel & T. Gustafson, Rutgers University, D. L. Kwong & J. Lee, University of Texas at Austin, T. P. Ma, Yale University, D. Schlom, Penn State University, S. Stemmer, UC Santa Barbara

ABSTRACT

Considerable progress has been made in identifying materials and processes for high k gate stacks which meet the ITRS leakage requirements. Nitrided Hafnium silicates have been shown to possess the requisite thermal stability for equivalent oxide thicknesses (EOT) below about 1 nm. Gate electrodes of TaSiN, Ru, or Ru/Ta alloys also appear to meet the stability requirements and possess appropriate work functions.