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Tool Order: ASML receives belated US$108 million Xmas present from TSMC
ASML has had a great start to the New Year with several new orders
placed with the lithography equipment leader that total over US$108
million. TSMC has begun 2012 with a new wave of purchase orders with
leading equipment suppliers.
Read more >>Imec and ASML team on next-generation lithography for another 5 years
One of the longest technology partnerships in the semiconductor industry
is set to get longer after both imec and ASML agreed to extend work on
both immersion and EUVL development, for a further 5 years. The
agreement follows installations at imec’s 300mm R&D facility with
ASML’s NXT1950i immersion tool and its NXE:3300B, the successor of
ASML’s NXE:3100 preproduction tool that has been installed at imec,
earlier this year.
Read more >>Tool Order: RAVE wins multi-system order for reticle haze removal
A major independent device manufacturer has placed a multi-system
purchase order with RAVE for its ‘Rhazer’ haze removal systems for
reticles. The orders were given after an extensive in-fab evaluation of
the Rhazer haze removal technology, according to RAVE.
Read more >>Product Briefings
New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy
Product Briefing Outline: Applied Materials has introduced its
new ‘Applied Centura Tetra’ EUV Advanced Reticle Etch system. The new
systems is claimed to overcome a major hurdle to the adoption of EUV
lithography by solving the critical and unmet challenge of etching EUVL
photomasks with nanometer-level accuracy and world-class defect
performance to enable the fabrication of multiple new generations of
high-performance semiconductor chips at the 16nm node and below.
Read more >>New Product: ASML Brion’s Tachyon MB-SRAF enables OPC-like compute times
Product Briefing Outline: Brion Technologies, a division of ASML,
has launched a new product for its Tachyon computational lithography
platform. Tachyon MB-SRAF (Model-Based Sub-Resolution Assist Features)
is said to enable the high-speed, full-chip processing of advanced chip
designs with larger process windows, greater productivity, and lower
development costs than rule-based alternatives.
Read more >>ASML enhances NXT:1950i immersion lithography platform
Product Briefing Outline: ASML has introduced three new extensions for
TWINSCAN NXT platform that improve imaging, overlay and productivity.
The extensions enable chipmakers to manufacture smaller, faster chips
more cost-effectively. The first NXT:1950i system shipped in 2009 and
today more than 80 systems are in use by chipmakers around the world
manufacturing current state-of-the-art devices at resolutions of 45- to
32-nm.
Read more >>White Papers
Lithography efficiency: a cost comparison model
By Sven Grünzig, Nemotek Technologie, Rabat, Morocco
ABSTRACT
The paper presents a calculation model and conclusions with focus on the comparison of low-throughput and high-throughput lithography clusters via an analysis of the lithography Cost of Ownership (COO) and applied data of the Overall Equipment Efficiency (OEE) and Overall Factory Efficiency (OFE). The report will show that the published documents up to today are not sufficient to prove that a higher throughput necessarily leads to an advantage of the manufacturing effectiveness and that it is necessary to calculate and adapt it onto the chip manufacturer’s requirements. It will show metrics and a methodology for fab planners and equipment engineers to calculate the needed cluster throughput and to optimize the lithography efficiency. Furthermore, the calculation model presents a flexible method to identify not only the key drivers to run an efficient production, but also to easily compare different scenarios. Two examples are shown, with models evaluated with real data. This study might also be applicable to other semiconductor processing steps.
Edition 38: The holistic route to high yields at smallest feature sizes
By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole.