Online information source for semiconductor professionals



Gigaphoton opens new US regional headquarters in Beaverton, Oregon

21 March 2012

New Gigaphoton US headquartersGigaphoton, the high-performance DUV laser light provider is to move its business management, logistical and training centres to its US headquarters in Oregon. It is hoped that the decision will mean better service for its increasing number of installed bases. The company has increased laser installed bases 10 times since the company’s inception in 2008.


TSMC places blockbuster purchase order with ASML

08 March 2012
Confirming the recent demonstration of annoyance by Applied Materials, Mike Splinter that spending on lithography equipment was eating into his company’s sales opportunities; TSMC has placed its largest single order this year with ASML. Read more >>

SUSS MicroTec and GenISys team on mask aligner optimization

21 February 2012
In a bid to enable easier modelling of large numbers of different source shapes, SUSS MicroTec and GenISys are teaming to jointly offer their products for mask aligner equipment. The cooperation means that GenISys’ ‘Layout LAB’ has been enhanced to accurately model all available SUSS MicroTec mask aligner exposure optics, including the SUSS MO Exposure Optics technology. Read more >>

Product Briefings

SPIE 2012: Tachyon FMO provides effective hotspot repair for advanced mask correction

13 February 2012
Product Outline: Brion Technologies, a division of ASML, has launched the Tachyon Flexible Mask Optimization (Tachyon FMO), part of ASML’s Holistic Lithography portfolio. Tachyon FMO is claimed to enable the seamless use of multiple Optical Proximity Correction (OPC) techniques in a single mask tapeout, permitting the use of advanced and computationally intensive OPC in key local areas where they provide maximum benefit. Read more >>

New Product: Applied Materials new EUV reticle etch system provides nanometer-level accuracy

19 September 2011
Product Briefing Outline: Applied Materials has introduced its new ‘Applied Centura Tetra’ EUV Advanced Reticle Etch system. The new systems is claimed to overcome a major hurdle to the adoption of EUV lithography by solving the critical and unmet challenge of etching EUVL photomasks with nanometer-level accuracy and world-class defect performance to enable the fabrication of multiple new generations of high-performance semiconductor chips at the 16nm node and below. Read more >>

New Product: ASML Brionā??s Tachyon MB-SRAF enables OPC-like compute times

19 September 2011
Product Briefing Outline: Brion Technologies, a division of ASML, has launched a new product for its Tachyon computational lithography platform. Tachyon MB-SRAF (Model-Based Sub-Resolution Assist Features) is said to enable the high-speed, full-chip processing of advanced chip designs with larger process windows, greater productivity, and lower development costs than rule-based alternatives. Read more >>

White Papers

Lithography efficiency: a cost comparison model

21 October 2010

By Sven Grünzig, Nemotek Technologie, Rabat, Morocco

The paper presents a calculation model and conclusions with focus on the comparison of low-throughput and high-throughput lithography clusters via an analysis of the lithography Cost of Ownership (COO) and applied data of the Overall Equipment Efficiency (OEE) and Overall Factory Efficiency (OFE). The report will show that the published documents up to today are not sufficient to prove that a higher throughput necessarily leads to an advantage of the manufacturing effectiveness and that it is necessary to calculate and adapt it onto the chip manufacturer’s requirements. It will show metrics and a methodology for fab planners and equipment engineers to calculate the needed cluster throughput and to optimize the lithography efficiency. Furthermore, the calculation model presents a flexible method to identify not only the key drivers to run an efficient production, but also to easily compare different scenarios. Two examples are shown, with models evaluated with real data. This study might also be applicable to other semiconductor processing steps.


Edition 38: The holistic route to high yields at smallest feature sizes

08 January 2009

FT38By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole.


Sources of overlay error in double patterning integration schemes

01 March 2008
David Laidler, Philippe Leray, Koen D’Havé & Shaunee Cheng, IMEC, Leuven, Belgium Read more >>