R. Singh, T. Boland, R. Mulye, G. Gaur, J.Steelman, D. Arya, N. Srinidhi and P.Deshmukh, Holcombe Department of Electrical and Computer Engineering and Center for Silicon Nanoelectronics, Clemson University, South Carolina, USA

ABSTRACT

Directed self-assembly (DSL) has been projected as a potential solution to the critical dimension limit faced by conventional lithography techniques. In this paper we review the literature data on directed self-assembly to investigate the challenges in application of self-assembly techniques for mainstream semiconductor manufacturing.  Based on fundamental considerations and process-induced defects of DSL, it is highly unlikely that DSL will ever enter mainstream semiconductor manufacturing.

Iris Mäge & Uwe Seifert, Qimonda AG, Dresden; Barry Saville & Martin Tuckermann, KLA-Tencor GmbH, Dresden

ABSTRACT

With the introduction of sub-100nm design rules, and especially 193nm photolithography, the development of new monitoring strategies is becoming increasingly important and necessary as new materials, new tools and new process challenges are introduced. Micro after-develop inspection (µADI) is a big step forward for photolithography defect monitoring as well as for integrated process learning.

Michael D. Archuletta, Chris Constantine & Dave Johnson, Unaxis Semiconductors, Florida, USA

ABSTRACT

Wafer dimensions continue to accelerate downward towards ever smaller features and the legendary Moore’s Law is still valid for current silicon devices. As wafer IC dimensions approach the physical limitations of silicon physics, the lithography techniques used to print these patterns on silicon become very difficult to perform. This article describes advances in this area down to 65-nm sizes.

Uzodinma Okoroanyanwu, AMD, USA; Remo Kirsch & Marcel Grundkowski, AMD Fab 36, Germany; Rene Wirtz & Wolfram Grundke, AMD Saxony LLC, Germany

ABSTRACT

The product pilot lines of the leading-edge IC fabs in the world today are fine tuning their immersion lithography processes for patterning devices at the 45nm technology node, in  preparation for high volume production in 2008. Within a relatively short time,  immersion lithography has made the transition from a mere research curiosity just three years ago to a technology that has shown significant and demonstrable device yield, and is now poised for large scale deployment across the 45nm node device product line. This is a remarkable achievement, which underscores the enormous progress made in the realm of defectivity and overlay control – the twin achilles heels of immersion lithography.

By Mark Thirsk and Mike Corbett, Linx Consulting LLC, USA

ABSTRACT

For at least the last 20 years, lithography has enabled the increase in density that has sustained the rapid increase of functionality that has been key in the development of the electronics industry.  Today, lithography faces physical, chemical and business challenges in delivering the patterning densities required by the ITRS (International Technology Roadmap for Semiconductors). The pressure to achieve the next node (even in name) before the competition accelerates the development progress from an anticipated 3-year to a 1.5- or 2-year cycle is intense.  This pace to improve resolution puts huge strains on the lithographer, and indeed on all involved in transferring the pattern to the substrate.  However, the need to meet future requirements is leading to several new trends in lithography and patterning.

By Monique Ercken, Roel Gronheid, Ivan Pollentier and Philippe Leray, IMEC, Belgium

ABSTRACT

193nm immersion lithography is rapidly moving towards industrial application. A large number of tools has been installed worldwide and they, of course, will require immersion-capable processing to be available. Resist processes without protective topcoats are the favored solution for introduction into mass production, from a cost-of-ownership perspective. This approach adds at least two extra constraints to the list of resist requirements: low leaching and high dynamic contact angle. Various components in the resist show (before and/or after exposure) at least some solubility in water and therefore are likely to leach into the water. This can be a source for lens contamination and resist defectivity. Next to that, the dynamic ‘receding’ contact angle is considered as one of the key parameters to control the amount of water droplets left behind on the wafer surface after exposure. These factors make the selection of a resist for processing without a topcoat as a barrier layer quite challenging, because now minimized leaching, acceptable contact angle and superior overall litho performance (at half-pitches as small as 45nm) are to be met simultaneously. In this paper, we will address whether current state-of-the-art dedicated immersion resists without topcoat are ready for use in production. An overview will be given on the performance of these materials and for some selected parameters a comparison will be made with a process including a topcoat.

By Eitan Herzel and Mike Adel, KLA-Tencor Corporation, Israel

ABSTRACT

Overlay control has always played an important role in semiconductor fabrication, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind implies short circuits and connection failures, which in turn impact fab yield and profit margins. The importance (and associated difficulty) of controlling overlay has grown exponentially since 90nm, but robustness of overlay measurements has become especially critical as logic and memory IC manufacturers now ramp into high-volume 45nm production, where overlay budgets are shrinking fast (see Figure 1) from a relatively relaxed 30% of design rules down to 10% or even less.

By Terrence E. Zavecz, TEA Systems, Philadelphia, USA

ABSTRACT

The International Technology Roadmap for Semiconductors' history details the growing complexity of device design and the latest device-manufacturer's techniques for tuning their process for each new design generation.  In spite of the current desire to incorporate techniques termed 'Design for Manufacture' into manufacturing, simulations and the design cycle, they do little more than optimize feature quality for ideal exposure conditions while testing for shorts, opens and overlay problems over process variations.

Stefan Hempel, Steffen Volt & Wolfram Grundke, AMD, Dresden, Germany

ABSTRACT

Lithography scanners represent the most cost-intensive tools in a semiconductor facility. Productivity improvements on litho clusters not only increase the whole lithography productivity but also enhance the entire fab performance. To ensure a cost-efficient lithography process, the scanner should always represent the internal bottleneck within a linked lithography cell. Therefore, it is specifically important to maximize the scanner performance and its output. This paper provides an overview of methods and approaches to increase the productivity of linked lithography cells. 

Peter Rabkin, Michael Hart & Daniel Gitlin, Xilinx, Inc.

ABSTRACT

Leading fabless companies produce designs for cutting edge technologies almost on a par with leading integrated device manufacturers (IDMs). Foundries have evolved from making devices one to three nodes behind IDMs to funding leading-edge R&D and manufacturing chips using the most advanced processes. The key fabless/foundry challenge - how to produce manufacturable designs for cutting edge technology nodes to meet time-to-yield and time-to-volume requirements - is being overcome by an extensive effort broadly called Design For Manufacturability (DFM). Different from IDM requirements, fabless DFM requires addressing a number of additional issues, such as obtaining and utilizing proprietary manufacturing information in the course of the design. That, in turn, requires deep understanding of process-to-design interactions, new process characterization and modeling methodologies, EDA tools, data structures, process models, encryption techniques, etc. Solving these issues and enabling sufficient information flow between design and manufacturing is critical for the overall competitiveness of the fabless/foundry business model.