Reiner Missale, Qimonda AG, Germany
 
ABSTRACT 

300mm technology has forced the semiconductor industry to take a broader perspective on the classical understanding of production and Shop-Floor Control. As a consequence, the focus shifted from the perspective of Transport Automation and Manufacturing Execution Systems to the integrated Factory, viewing all involved elements for semiconductor production. In pre-300mm, the process-engineering domain saw limited overlap to production logistic and transport. Today the linkage and integration of process control and shop-floor control and production logistic is acknowledged as a key factor for operational excellence. These are the Enabling Technologies for the high-end “Manufacturing Operations Management”.

By Gino Crispieri, ISMI, Texas

ABSTRACT

Timing requirements placed on maunfacturing systems are becoing increasingly stringent in the semiconductor industry.  Traditionally, these manufacturing systems have been implemented in a centralized architecture in which the timing constraints were met by paying careful attention to programming combined with the use of communication technologies with deterministic latency.

In recent years, an increasing number of manufacturing systems have used distributed computer architectures and relied on mainstream networking technologies.  In particular, Ethernet-based communications are becoming more common in manufacturing applications.  This has led to alternative means for enforcing the timing requirements in such systems.  One such technique is the use of system components that contain real-time clocks, all of which are synchronized to each other within the networked system.

Robert Bixby, ILOG Inc., & Rich Burda & David Miller, IBM, USA

ABSTRACT

Fully automated 300mm manufacturing requires the adoption of a real-time lot-dispatching paradigm. Automated dispatching has provided significant improvements over manual dispatching by removing variability from the thousands of dispatching decisions made every day in a fab. Real-time resolution of tool queues, with consideration of changing equipment states, process restrictions, physical and logical location of WIP, supply chain objectives and a myriad of other parameters, is required to ensure successful dispatching in the dynamic fab environment.

Discussion panel: Harvey Wohlwend, Manager, ISMI; Mark Pendleton, Principal Software Architect, Asyst Technologies; Michael Arnold, Managing Director and Program Manager of fab services, PEER Group.

ABSTRACT

Building, ramping and operating 300mm fabs takes significant capital expenditure that puts pressure on all concerned to rapidly achieve desired returns on investment.  The ability to rapidly ramp with sustainable high yields has become an essential aspect of 300mm fab operations.  Interface A was conceived by the semiconductor industry to address important aspects of tool/process data collection that previous standards (SEC/GEM) were not designed to effectively handle.  With experience garnered from the standards' efforts to migrate to 300mm wafer processing, Interface A has been developed in quicker time with less revisions.  However, the adoption of this vastly superior data port technology in 300mm fabs has not mirrored the pace of its development cycle.  This discussion panel article brings together key players in the development and deployment of Interface A in an effort to understand how far down the road it is to fab-wide adoption.

Mark Osborne, Editor-in-Chief, Semiconductor Fabtech

Michael Corbett & Mark Thirsk, Linx Consulting LLC,USA

ABSTRACT

Today, most new logic and ASIC devices are being implemented with multiple copper interconnect layers put down with a dual damascene approach. This article will examine the state-of-the-art in copper CMP polishing for the 90nm node that is currently being ramped into highvolume manufacturing, and look forward to the challenges, needs and trends for the implementation of 65nm and 45nm half-pitch devices.  We also analyze forecasts of unit operations, discuss the dynamics within the supply side of the CMP consumable industry, and look at how novel technologies such as ECMP may impact both users and suppliers. 

The discussion topic format is new to Semiconductor Fabtech. It consists of individual experts in a field providing separate comment on a major technology issue. All contributors' views are presented separately and formatted clearly to show the differences compared to a co-authored style paper.

Walt Trybula, The Trybula Foundation Inc., & Brian Grenon, Grenon Consulting, Christian K. Kalus, SIGMA-C, Nigel Farrar,Cymer Inc., Frank D. Masciocchi, Litel Instruments, Martin McCullum, Nikon Precision Europe, Mircea Dusa, ASML, Rainer Pforr, Infineon Technologies.

ABSTRACT
As the lithography is both the most costly and critical process towards fully functioning semiconductor devices, it is obvious that developments within the lithography field are closely followed and analyzed. This year at the SPIE Microlithography Conference it became clear that a major shift in lithography tool and process techniques is required to continue scaling as befits Moore's Law. EUV lithography is not going to be ready for Intel's needs at the 32nm node while immersion lithography has not ‘matured' enough for the chip giant to ‘risk' production for its introduction of 45nm node IC devices. Instead, Intel plans to retain the use of ‘dry' 193nm ArF DUV tools, while adopting a Double Patterning (DP) imaging regime through to the 32nm node. Although there are various DP strategies possible, few experts in the field believe that some form of throughput, cycle-time and cost impact on fab operations will not occur. Although not all leading-edge IC manufacturers may pursue a DP strategy, it would now seem certain that everyone will need to look deeply into the pros and cons before making such critical manufacturing decisions. We are very pleased to have been able to assemble in this discussion piece, a group of experts within the lithography discipline to cover some of the key issues surrounding DP strategies, especially at such short notice, so soon after the SPIE Conference. 

Matthew Purdy, Advanced Micro Devices, Austin, TX, USA

ABSTRACT

The economics of bringing a new, 300mm semiconductor factory online are enormous, with capital costs in the billions of dollars. Such large initial capital outlays in the highly competitive semiconductor industry require a rapid return on investment. Such a return can only be done by operating factories at high levels of efficiency and predictability. 

Ashwin Ghatalia, Kranthi Adusimilli, Dave Dyer, Walter Worth, Robert Wright, Phil Naughton, Joel Barnett & Steve Burnett, International SEMATECH, Austin, Texas

ABSTRACT

The International Technology Roadmap for Semiconductors (ITRS) lists several major challenges for IC factory integration. Two of them are factory flexibility and management of factory complexity. This article compares single-wafer clean to current batch processes from an overall IC factory perspective. Tools, factory-level investments, facilities, cycle time, factory logistical impacts and environmental issues are addressed. The influence of different equipment configurations is also investigated. 

Mark Osborne, Editor-in-Chief, Semiconductor Fabtech

ABSTRACT

During the 16th Annual IEEE/ SEMI Advanced Semiconductor Manufacturing Conference, held during SEMICON Europa, 11-12th of April 2005, presentations from Intel, in particular, provided insight into the constantly evolving world of 300mm fab automation. The drive towards fully integrated and highly automated operations to improve cycle times, yield and overall manufacturing efficiencies is seen as a competitive advantage. We review the key presentations at this years ASMC Conference that discussed 300mm fab automation practisesand future developments. 

Mark Osborne, Editor-in-Chief, Semiconductor Fabtech

ABSTRACT

During every January the major market forecasting firms and their leading market analysts present their forecasts of the semiconductor industry for the year ahead.With 2004 proving to be a very good year for the industry it is rather surprising that a good deal of pessimism about 2005 is evident. A round up of 2005 projections put the majority of forecasters in the pessimistic bracket while two forecasters in particular buck this trend with strong optimistic projections for the year ahead. Though its long been said, that "bad news sells newspapers," we focus attention on the two optimistic forecasts (Future Horizons, VLSI Research) for reasons that are not as obvious as you would think!

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Len Jelinek, iSuppli Corp.

ABSTRACT

Semiconductor investors and industry watchers began 2004 with high expectations. As they saw it, the chip market was a depressed sector that had a strong outlook and that promised increasing demand and limited supply. With bullish forecasts, rising average selling prices (ASPs) and increased profitability for chipmakers, what could go wrong?  But before you could say déjà vu 2000, market conditions changed - and sentiment among industry participants quickly soured. 

John E.J. Schmitz, Chief Operating Officer, Manufacturing Technology, International SEMATECH Manufacturing Initiative, Austin, Texas, USA

ABSTRACT

This article discusses the escalating costs associated with manufacturing advanced electronic circuits. Emanufacturing will have to play a much larger role in this manufacturing if the requirements are to be met on schedule. It is concluded that all players in semiconductor manufacturing will have to adopt this approach if they are to remain competitive. 

Bill McClean, President IC Insights, Inc, Scottsdale, AZ, USA

ABSTRACT

Figure 1 provides worldwide capital spending trends from 1995 through 2003 and a forecast for 2004 through 2008. As shown, semiconductor industry capital spending is not expected to exceed 2000's level until the peak of the next IC industry cycle in 2008! When looking at the per cent change line in Figure 1, it is evident that IC insights believes that the historically volatile trends in capital spending outlays will continue through 2008. 

Thomas J. Sonderman, Advanced Micro Devices, Austin, TX, USA

ABSTRACT

The demands on semiconductor manufacturers have never been greater than they are today. Companies are challenged to meet market demand by delivering increasingly sophisticated products in high volume, on time and more cost-effectively than ever before. The economy of scale makes a conversion to 300-mm wafers ultimately beneficial, but there is an inherent risk associated with the transition. With the value of each 300-mm wafer more than double that of 200-mm wafers, 300-mm manufacturing demands a level of process improvement that effectively keeps costs low while maximizing the value of each wafer.

Jennifer K. Robinson, FabTime, Inc.

ABSTRACT

FabTime is focused on improving wafer-fab cycle times through consulting, training, and our webbased digital dashboard software. For the past two years, we have conducted an informal survey of the roadblocks to great fab cycle-time performance. To date, the top response has been "equipment downtime". In this article, we discuss several best practices for improving fab cycle time by focusing on tool uptime. 

R. Sturm & K. Reddig, Fraunhofer Institute Manufacturing Engineering and Automation Stuttgart, Germany. D. Glüer, Advanced Micro Devices Saxony LLC & Co. KG, Dresden, Germany

ABSTRACT

Planning and operating automated material handling systems (AMHS) for microelectronics and semiconductor manufacturing have become increasingly important for modern high-volume production lines. As a service system for the manufacturing process, reliable material supply to the process equipment is mandatory, and the scope of operating an AMHS is on the prompt.