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EHS The Environmental, Health & Safety (EHS) section concerns itself
with these issues within advanced volume manufacturing CMOS based
facilities around the world. From water recycling strategies and
technologies to abatement topics this section provides senior fab
managers and EHS engineers with case studies, new technologies and
sector overviews useful for things such as benchmarking.
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Dec 20, 2006 at 11:06 AM |
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Mike Yurconic, Intel Technology Development EHS, Hillsboro, Oregon ABSTRACT In the mid-1980s, Intel documented its Design for EHS philosophy for process tools and developed a set of internal design requirements with which suppliers must comply. After Sematech’s industry-wide guidelines became available, Design for EHS evolved into the New Equipment Procurement Process (NEPP). The major element of the NEPP requirements is tool conformance to SEMI S2, Environmental, Health and Safety Guideline for Semiconductor Manufacturing Equipment and SEMI S8, Safety Guidelines for Ergonomics/Human Factors Engineering of Semiconductor Manufacturing Equipment. Tool suppliers are required to provide copies of the SEMI S2/S8 reports for all first-of-a-kind tools purchased by Intel-to-Intel EHS with the expectation of 100% conformance. NEPP has been extremely successful, reducing the number of design-related EHS issues associated with the installation and operation of process tools in Intel fabs virtually to zero. Write Comment (0 comments) |
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Jun 25, 2006 at 07:27 PM |
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Scott Stewart, Intel Corporation, Hilsboro, OR, USA
ABSTRACT
This article explores the challenge faced by semiconductor manufacturing facilities to reduce their environmental footprint and avoid regulatory constraints. Wafer fabs continue to increase in size and complexity, while regulatory emissions limits continue to shrink. The focus is on volatile organic compound emissions (VOCs), which pose the most likely constraining air permit limit. Areas covered include common air permit limits and requirements, analysis of VOC sources at a typical semiconductor facility and examples of wins from Intel's VOC reduction toolbox including improved waste management procedures. Finally, attention is given to remaining emissions problems and what must be done to ensure future manufacturing capability. Write Comment (0 comments) |
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Mar 09, 2006 at 09:41 AM |
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Chin-Tsao Yang, Shu-Hou Wang, Milton Li, Wu-Hsiung Fu, & Max Chen, Facility department, Powerchip Semiconductor Corporation
ABSTRACT During the design of PSC's Fab 12A, whole system efficiency was promoted, particularly in terms of power consumption. One of the most effective energy-saving projects was to lower the temperature of cooling water to promote the operational efficiency of the chiller system. This measure resulted in power savings for the chiller system of about 15 percent or some 7GWH of electricity a year. Write Comment (0 comments) |
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Mar 09, 2006 at 09:37 AM |
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Philip Naughton, Freescale Semiconductor Inc. Assignee at SEMATECH, Austin, Texas, USA
ABSTRACT Resource consumption directly impacts the cost of semiconductor manufacturing and indirectly contributes to environmental pollution. Several resource-conservation projects and surveys since 1996, have been performed at Sematech member companies and suppliers demonstrating significant reductions in tool and resource consumption are possible but are they enough? The ITRS roadmap continues to challenge new fabs to meet ever-decreasing energy goals. The World Semiconductor Council and SEMI have issued their White Paper on Energy suggesting normalized energy reductions for wafer fabs. In order to achieve measurable reductions both factory owners and tools suppliers will need to baseline their energy consumption and establish specific targets for improvement. Write Comment (0 comments) |
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Dec 14, 2005 at 04:38 PM |
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Pablo Ruiz, RFAB Process Waters and Drains Project Manager, Texas Instruments, Dallas, Texas, USA ABSTRACT In the first quarter of 2004, TI began design of its new wafer fabrication facility in Richardson, Texas, five miles north of the main Dallas campus. We reexamined how to competitively build and operate this new facility and reconsidered all of our old paradigms of how we should build a wafer fab. By the end of the design process we determined that we could build a competitive fab while reducing first costs and ongoing operational costs. In this article I will be discussing some of these design elements in TI's newest fab we now call RFAB. Write Comment (0 comments) |
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Jun 21, 2005 at 01:02 PM |
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Mark Osborne, Editor-in-Chief, Semiconductor Fabtech ABSTRACT Energy-consumption-reduction strategies are nothing new, however, such energy-saving efforts have not been successful in reducing the overall energy consumption of the semiconductor industry. The total number of operational fabs continues to increase due to the continued growth of the industry. The number of "Mega" 300-mm fabs (50 by the end of 2005) [1] that have significantly higher energy consumption levels is also rising. The world is also coming to terms with the realisation that energy costs will continue to rise as consumption of fossil fuels (regarded as the cheapest energy source) is under sustained supply/demand pressure. Write Comment (0 comments) |
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Feb 20, 2005 at 12:59 PM |
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Michael W. Wismer & Richard E.Woodling, USFilter, Milpitas, CA, USA
ABSTRACT The Copper Select™ process is being used at many semiconductor Fabs around the world to successfull treat copper-bearing CMP wastewaters. The patented process removes copper from wastewater without removing the CMP slurry particles. Studies have shown the process to be very successful with most commercially available copper slurry formulations. Write Comment (0 comments) |
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Dec 11, 2004 at 12:27 PM |
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Jay M. Dietrich, Chemical, Environmental and Utility Systems, IBM Burlington, USA
ABSTRACT As the semiconductor industry has transitioned from aluminum to copper metallization, it has been necessary to overcome many technical challenges in the device-manufacturing process. The required process changes for the chemical mechanical planarization (CMP) process have had a significant impact on the characteristics of the process wastewaters generated by the CMP process. Write Comment (0 comments) |
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Sep 21, 2004 at 12:23 PM |
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Walter F.Worth, International SEMATECH, Austin, Texas, USA ABSTRACT For the last three years, International SEMATECH has had an active program to identify potential environment, safety, and health (ESH) impacts associated with the development of advanced lithography technologies. The focus has mainly centered on 157-nm lithography, 193-nm immersion lithography, and extreme ultraviolet (EUV) lithography. Through close collaboration with the technologists in SEMATECH's lithography division, it is hoped that ESH concerns can be identified and addressed during the early stages of the materials selection and process/tool development, well in advance of their introduction into high-volume manufacturing (HVM). Write Comment (0 comments) |
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Jul 21, 2003 at 09:52 AM |
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Alan E. Rimer, Black & Veatch International ABSTRACT The world's water resources are becoming strained and many in the world have limited access to potable water. During the fast-paced growth of the semiconductor industry over the last several decades, water has become a precious commodity. This has happened in spite of the fact that in many cases the industry has chosen to locate in arid climates where water is scarce. Why should the semiconductor industry consider reuse? As the demand for scarce water resources grows, and communities face impaired streams that require higher levels of wastewater treatment and required recharge of groundwater aquifers, reuse will become more important. The question is whether the industry can rise to the occasion and embrace reuse. Write Comment (0 comments) |
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