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TSMC joins European sub-45nm research |
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Oct 18, 2005 at 11:38 AM |
By Dr Mike Cooke
The world's leading foundry Taiwan Semiconductor Manufacturing Company
(TSMC) is to become a core partner in the sub-45nm CMOS research
programme of IMEC, the European semiconductor process research centre
in Belgium.
TSMC is the eighth IC manufacturer to join the research. The other IC
producing partners are Infineon, Intel, Matsushita/Panasonic, Philips,
Samsung, STMicroelectronics and Texas Instruments. The collaboration
uses IMEC's state-of-the-art 300mm research facilities in its efforts
to conquer the challenges set out in the International Technology
Roadmap for Semiconductors (ITRS).
IMEC says that it has now gathered the full scope of companies involved
in the processing chain including integrated device manufacturers
(IDMs) in the logic as well as the memory arena, the largest foundry
and the largest equipment suppliers.
The research centre reports that the front-end-of-line segment of its
300mm research platform has been up and running since July of this
year. The installation of the back-end-of-line is gaining momentum
thanks to strategic agreements with leading equipment manufacturers.
The research focus has shifted from the 45nm node to 32nm and beyond
with programs on advanced lithography, front-end-of-line, advanced
interconnect solutions, cleaning and contamination control, and
exploratory research on emerging devices.
The advanced lithography program currently focuses on 193nm immersion
lithography, at present on an ASML XT 1250i scanner, and soon, as of
mid 2006, on an ASML XT1700i scanner with hyper-NA of 1.2. Meanwhile,
IMEC is also starting up EUV research based on a strategic agreement
with ASML to install an early full-field alpha demo tool.
Front-end-of-line research program package consists of planar CMOS
device integration research (high-mobility layers, ultra-shallow
junctions and high-k gate-stack integration), research on advanced
high-k and metal-gate-stack materials and processes, and non-planar
CMOS device research with a focus on FINFETs.
The interconnect segment will further explore the limits of Cu/low-k
scaling. In addition, it now contains a more speculative sub-program on
the potential of 3D stacked ICs.
With the shift towards 32nm and beyond, more emphasis will also go
towards emerging device concepts - in the mid-term, germanium and III-V
devices, and, for the post-CMOS era, carbon nanotubes and
semiconducting nanowires.
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