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19th Edition: A 0.18-µm logic-based MRAM technology for high performance nonvolatile memory |
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Jan 20, 2005 at 10:44 AM |
MRAM Development Alliance, IBM/Infineon Technologies, IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533, USA
ABSTRACT
This paper discusses the fabrication of a 2-kb array test chip with a
1.66-µm2 cell and a corresponding 128-kb MRAM (magnetoresistive random
access memory) with a 1.4-µm2 cell. The technology features a 1 transistor 1 MTJ (magnetic
tunnel junction) cell in a 0.18-µm, 3-level Cu metallization
logic-based process. Outlined here is a yield analysis of the read
operation, which is governed by the MTJ resistance distribution
function and a systematic study of the write operation. MRAM
functionality, with a checkerboard disturb pattern, was obtained after
process optimization. Write endurance tests did not show degradation of
the cell properties.
 07 - A 0.18-µm logic-based MRAM technology for high performance nonvolatile memory applications
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Wafer Processing 
