Online information source for semiconductor professionals

A.R. Sitaram#, D.W. Abraham*, C. Alof#, D. Braun#, S. Brown*, G. Costrini§, F. Findeis#, M. Gaidis§, E. Galligan*,W. Glashauser#, A. Gupta*, H. Hoenigschmid#, J. Hummel§, S. Kanakasabapathy*, I. Kasko#,W. Kim#, U. Klostermann#, G.Y. Lee#, R. Leuschner#, K-S. Low#, Yu Lu*, J. Nützel#, E. O’Sullivan*, C. Park#,W. Raberg#, R. Robertazzi*, C. Sarma#, J. Schmid#, P.L. Trouilloud*, D.Worledge*, G. Wright*,W.J. Gallagher*, & G. Müller#, MRAM Development Alliance, IBM/Infineon Technologies, IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533, USA (# Infineon Technologies, § IBM Microelectronics Division, *IBM Watson Research Center).

ABSTRACT

This paper discusses the fabrication of a 2-kb array test chip with a 1.66-μm2 cell and a corresponding 128-kb MRAM (magnetoresistive random access memory) with a 1.4-μm2 cell. The technology features a 1 transistor 1 MTJ (magnetic tunnel junction) cell in a 0.18-μm, 3-level Cu metallization logic-based process. Outlined here is a yield analysis of the read operation, which is governed by the MTJ resistance distribution function and a systematic study of the write operation. MRAM functionality, with a checkerboard disturb pattern, was obtained after process optimization. Write endurance tests did not show degradation of the cell properties.