Online information source for semiconductor professionals

Simulation for DUV-Lithography

Popular articles

Micron moving fast on Hynix in Q208 NAND flash rankings, says iSuppli - 19 August 2008

Numonyx to close California Technology Center - 12 August 2008

Qimonda starts major reorganization: exits PC DRAM market - 13 October 2008

Micron close to Inotera share purchase, says Gartner - 06 October 2008

Applied Materials sees higher CapEx spending for 2009 - 15 August 2008

WOLFGANG HENKE, Fraunhofer Institut Siliziumtechnologie, Itsehoe, Germany

ABSTRACT

Deep-UV (DUV) lithography using 248 and 193 nm exposure wavelength will be the microlithography technology of choice for the manufacture of advanced memory and logic semiconductor devices for the next years. For many companies DUV-lithography with 248 nm sources is becoming mainstream technology. To support introduction of this technology into wafer fabs and to ramp up or improve production yield, the use of simulation tools is a valuable means. Although concepts are, in principle, similar to traditional i-line or g-line lithography, exposure technology and imaging mechanisms of DUV resists are substantially different. The payoff from introducing DUV lithography will be the ability to manufacture devices using optical lithography for device generations having minimum dimensions of 0.12 μm or even below. This article will review some of the key issues to be tackled when applying simulation tools in current technology development. Issues concerning influence of the stepper or scanner lens, resist materials and resolution enhancement are discussed.
Download Please login to download the paper. No account yet? Please register. It's free!

Related jobs

Electrical Engineer III - MKS Instruments, Inc. - Andover, 07 October 2007

Principal Embedded Software Engineer - MKS Instruments, Inc. - Wilmington, 05 September 2007

Analog IC Design Engineer - AMI Semiconductor - Austin, 10 August 2007

Analog Design Engineer - AMI Semiconductor - Sunnyvale, 10 August 2007

Electrical engineering - Axcelis - Beverly, 10 August 2007

Related articles

Mask Error Factor and Critical Dimension Budgets for Sub-Half Micron CMOS Processes - 01 March 2000

New Product: Brion accelerates Tachyon DFM capabilities for sub 45nm designs - 26 February 2007

Spectroscopic Ellipsometry (SE) for materials characterization at 193 and 157nm - 01 September 2002

New Product: Brion’s new Tachyon M3D accounts for 3D imaging effects on photomasks - 22 September 2006

Tool Order: GenISys adds more research labs to Layout BEAMER software - 07 March 2008

Reader comments

No comments yet!

Post your comment

Name:
Email:
Please enter the word you see in the image below: