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New Product: Full-chip lithography simulation |
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Oct 04, 2005 at 04:19 PM |
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Product Briefing Outline: Brion Technologies has launched its
"Focus Exposure Modeling" (FEM) system, for one-model, full-chip, full
process window lithography simulation applications. FEM is designed to
simulate real-world lithography manufacturing processes before
photomask or wafer production begins.
Problem: The International Technology Roadmap for Semiconductors
(ITRS) identifies full-chip lithography simulation as a must-have
technology for sub-90nm technology nodes, when device developers rely
on complex optical proximity correction (OPC) and other resolution
enhancement techniques (RETs) to ensure devices can be manufactured as
designed. In this environment, weak spots in the circuit layout design
become an increasingly pronounced problem. Such weak spots are
exceptionally sensitive to process variation, and are thus prone to
fail. Without the ability to simulate lithography processes accurately
across the full process window, these weak spots are extremely
difficult (if not impossible) to prevent. If not caught before
production begins, weak spots can result in yield hits, systematic
design failures, delayed time to market and, ultimately, substantial
losses in revenue.
Solution: Brion's FEM system offers a new approach to full-chip
lithography simulation. The FEM product allows users to create a
single, comprehensive model of the lithography process across the
entire focus and exposure window. To achieve accurate simulation over
the real-world process window, FEM employs first-principle,
physics-based modeling techniques at full-chip capacity and throughput.
Until now, production fabs relied on full-chip models that run only at
nominal focus and exposure, leaving significant room for error and risk
of yield loss.
Applications: Lithography & photomasks.
Platform: Brion's FEM system extends the company's "Tachyon"
platform, and represents a foundational capability to Brion's new
Lithography Manufacturability Check (LMC) system. The Tachyon LMC
solution allows users to conduct full-chip, model-based inspection of
chip designs to predict the exact areas on a mask that are most likely
to fail due to lithography process variations. The combined FEM-LMC
system uses Brion's proprietary Tachyon computational lithography
platform, which incorporates advanced algorithms that combine
image-based simulation with EDA-style polygon and contour-based
geometry processing.
Availability: October 2005 onwards
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Product Briefings 
