Intel Corporation is well known to journalist for its
minimalist information on just about everything it does as a company. But in
the field of process technology it reigns supreme in telling us just about zilch!
At technical symposiums Intel is adept at conforming to the
proceedings guidelines on presenting papers. Intel more times than I can
remember, goes on to discuss a particular process that is already a year or two
out of date or is actually something they discarded for actual internal
production but thought it would be nice to share the work with its peers.
Of course we all
know how Intel justifies its actions but there is a level of detail it could
easily move towards and one that most other IC manufacturers seem prepared to
accept.
A press release from Intel appeared Tuesday that touted its
new ultra low power process technology that would be added to its 65nm process
portfolio. We all know how important power consumption and heat generation have
become to microprocessors in last couple of years and Intel should know better
than any chip manufacturer as they have mostly been responsible for the problem
in the first place!
Not that I was hoping the press release would actually
"reveal" anything of substance about the latest process tweaks, heaven forbid,
it would have taken me weeks to recover!
But its still shocking that Intel feels its quite acceptable
to push out a press release of such poor quality.
As the release was clearly meant to be one about process
technology (it had that in the headline) it took Intel seven (7) paragraphs of
dumbed down chit-chat before it actually said anything about the process
technology behind the move to improved lower power consuming devices!
Then it gets better, as three short paragraphs that included
(141) words attempted to tell us all about what is actually enabling the seven
paragraphs that preceded it.
Intel said that its was using a "second generation" strained
silicon process to achieve the desired results. That's actually all they
revealed! Yes, they also mentioned they were using transistors with a gate
length of 35nm and low k dielectrics, but as it's a 65nm device, the first fact
its obvious while the second is a no-brainer since the 90nm era, Doh!
Also consider that a year or more ago Intel "revealed" its
65nm technology to the press and stated then that the beauty of using strained
silicon was that it was scalable for several generations that included the 65nm
node. As 65nm comes after 90nm this must equal "second generation." Gosh! I
never thought I was good at maths, but thanks to Intel I think I am!
So in reality, Intel not only failed to "reveal" anything,
it simply regurgitated year old information. Perhaps that's why they dumbed
down the whole press release as they obviously think we are stupid!
If you want to know a very, very tiny bit more information
about the process tweaks, go to EETimes website, where Mark LePedus tells you
what was said in a briefing Intel gave before the release went out. But I warn
you, don't expect much OK!
Update: At Tom's Hardware, you can see even more detail about the new process,
click here
http://www.tomshardware.com/hardnews/20050920_161415.html
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| Senior Technical Program Manager (Dublin, Ireland, 02/04/2008) | | Senior Embedded Design Support Engineer (Shannon, Co Clare, Ireland, 19/03/2008) | | Embedded Support Engineer (Intel Shannon, Co Clare, Ireland, 19/03/2008) | | Senior Component Design Engineer (Intel Shannon, Co Clare, Ireland, 19/03/2008) | | Sales Engineer (Stuttgart, 16/08/2007) | |