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Arkadii Samoilov and Yihwan Kim, Applied Materials, USA

ABSTRACT

Elevated source/drain epitaxial Si deposition (on bulk and SOI substrates) and recessed epitaxial SiGe ultra-shallow junction techniques for logic MOSFETs, elevated source/drain and contact plug fill integration schemes for DRAM, self-aligned deposition of the base and spacer of hetero-junction bipolar transistors – these methods are increasingly used by chip manufacturers to boost performance of semiconductor devices. Productionworthy, safe, reliable equipment and process solutions, with tight control of deposition results are required to support the industry’s shift towards using selective epitaxy.