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V. Vartanian, B-Y Nguyen, A. Thean, D. Zhang, S. Zollner, T. White, M. Sadaka, B. Goolsby,
V. Dhandapani, J. Hildreth, L. McCormick, D. Theodore, Q. Xie, X-D Wang, M. Canonico,
M. Kottke, Z. Shi, L. Mathew, M. Zavala, C. Parker, H. Collard, L. Prabhu, R. Rai, S. Murphy,
P. Montgomery, S. Kalpat, M. Ramon, V. Adams, J. Jiang, J. Chen, V. Kaushik, M. Sadd, A. Barr,
A. Vandooren, D. Pham, V. Kolagunta, M. Orlowski, N. Ramani, S. Vanketesan & J. Mogab,
Freescale Semiconductor, Inc., Advanced Products Research and Development Laboratory, Austin, Texas, USA

ABSTRACT

The semiconductor industry has traditionally relied on reducing transistor dimensions such as gate length and gate oxide thickness to improve circuit performance. However, as gate lengths are reduced below 30 nm, new materials, processes, and device structures are required to overcome the fundamental physical limitations of conventional transistor materials and designs. For example, to attain enhanced carrier mobilities, biaxial tensile-stressed Si on relaxed SiGe on SOI or on bulk substrates is a viable option to increase drive currents. This article discusses issues with new materials being introduced into CMOS devices, and presents some potential solutions to enable high-performance, low-power CMOS for the 65-nm technology node and beyond.