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26th Edition: Integration of ALD TaN barriers in |
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Jun 21, 2005 at 11:10 PM |
W.F.A. Besling & M. Broekaart, Philips Semiconductors Crolles R&D, Crolles, France, V. Arnal, J.F. Guillaumond, A. Farcy & J. Torres, STMicroelectronics, Crolles, France, C. Guedj & L. Arnaud, CEA LETI, Grenoble, France
ABSTRACT
The downscaling of interconnect wiring is facing serious hurdles below 100nm feature size due to a nonlinear resistivity increase with decreasing linewidth. In order to investigate the increase of copper resistivity for the future technology nodes a novel hard mask spacer patterning technology was used to fabricate very narrow Cu inlaid interconnect trenches in a porous low-k dielectric. ALD TaN and PVD TaN films were deposited on a porous SiOC CVD dielectric material that received a pore-sealing treatment prior to barrier deposition.
26th Edition: Integration of ALD TaN barriers in porous low-k interconnect for the 45nm node and beyond; solution
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Wafer Processing 
