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H. S. Rathore, D. B. Nguyen, B. Agarwala, K. Chanda, R. G. Filippi, D. Edelstein, C. C. Yang, A. Cowley,W. Landers, M. Yoon, L. Clevenger, J. Demarest, C. R. Davis & C. A. Barile, IBM Systems and Technology Group, Hopewell Junction, NY, USA, C. K. Hu, IBM T. J.Watson Research Center, Yorktown Heights, NY, USA, F. Chen, IBM Systems and Technology Group, Essex Junction, VT, USA, D. Hawken, IBM Systems and Technology Group, Endicott, NY, USA

ABSTRACT

IBM has implemented copper because of its higher conductivity and scalability, to allow lower capacitances at higher current densities than Al, and to proceed to smaller dimensions at better reliability. The performance can be further enhanced by integrating low-k dielectric with copper to decrease capacitive load and RC delay of interconnects. Here we report the reliability stress result of 90-nm copper interconnects with CVD low-k as BEOL dielectric. This technology offers up to 12 levels of wiring, first as a W local interconnect, then eight in Cu/low-k, two in Cu/FTEOS, and one terminal Al- Cu level. All copper interconnects were processed by a dual damascene scheme except the first metal level (M1) which was single damascene. Data from stresses such as electromigration, stress migration, time-dependent dielectric breakdown (TDDB), thermal cycle and chip package interaction (CPI) on the Cu dual damascene structures in CVD low-k dielectric will be discussed. The results met or exceeded the reliability requirements and were equivalent to those obtained on a Cu-SiO2 interconnect scheme.