Prashant Majhi, (Assignee from Philips Semiconductors), Huang-Chun Wen, Gennadi Bersuker, George Brown, Byoung-Hun Lee, (Assignee from IBM), & H. Huff, SEMATECH, Austin, Texas, USA

ABSTRACT

The economics of IC manufacturing has driven the decrease of device sizes, while increasing the wafer size to bring down the cost per function for both mixed signal and digital processes. The cornerstone of all logic circuits, the transistor gate stack module, has been successfully scaled for about two decades using conventional materials, SiO2-type gate dielectric and poly-Si gate electrode. However, SiO2-type materials are reaching their physical limits of scaling due to high gate leakage associated with the direct tunneling of the carriers between the electrode and substrate, which is the dominant leakage mechanism in the case of ultrathin dielectrics.