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24th Edition: Development of multi-level interconnect technologies for 2nd generation 65nm node... |
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Dec 11, 2004 at 07:17 PM |
Yoshihiro Hayashi, System Devices Research Laboratories, NEC
ABSTRACT
NEC Corporation and NEC Electronics Corporation have succeeded in the development of multi-level Cu/low-k interconnects for second-generation 65nm-node VLSIs [1]. By improving the interconnect structure and dielectric material, reduction of the effective dielectric constant, keff, to the target value of keff equals 3.0 was successfully demonstrated, without degrading reliability. The interconnect power consumption is expected to be reduced by 16%->15%, and signal speed to be improved by 24%, as compared with 1st -generation structures [2].
24th Edition: Development of multi-levelinterconnect technologies for 2nd generation 65nm node VLSIs
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Wafer Processing 
