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FPO electronics makes news again, opens door for self-promotion, further reporting |
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Apr 09, 2008 at 02:47 PM |
Reporting from this week's Printed Electronics Europe show in Dresden, Germany--as well as recent news from Thin Film Electronics and other companies--has opened the door for some blatant self-promotion for an article I wrote for the March/April 2008 issue of Small Times, which has also been picked up in slightly tweaked form in the April 2008 Solid State Technology.
My feature focuses on coating and deposition challenges facing the developers and manufacturers of various types of flexible, printed, and organic electronics (FPOE) devices and includes input from people working in and around the trenches at Motorola, Uni-Solar/ECD, the Flexible Display Center, Aveso, Polymer Vision, and Hewlett-Packard.
HP Labs' Carl Taussig runs one of the more ambitious projects, a joint op with PowerFilm that seeks to develop a roll-to-roll (R2R) plasma process for producing active-matrix electrophoretic display backplanes on polymers, featuring an HP-developed patterning technology known as self-aligned imprint lithography, or SAIL.
I first heard--and reported on--Carl and his team's efforts at the 2007 version of the US Display Consortium's Flexible Electronics and Displays event, and was immediately intrigued by what they're building in those legendary Palo Alto labs. The program manager's willingness to share fairly detailed information and actually discuss specifics, as he did in presentations about the project at last year's and this year's Flex conference, also makes him a favorite of both FPOE techies and the journalists who cover them. So it's nice to see SAIL get additional coverage as it has this week on Semiconductor International's site.
But there's more to Carl and his group's story. With a somewhat limited word count, I didn't have space to include all of his comments in my Small Times/SST piece, so here are most of the Q&A outtakes from my email conversation with one of HP's FPOE pointmen.
TC: What do you see as the key challenges moving forward, as you scale from R&D to pilot line, and from pilot to volume manufacturing?
CT: As we increase the size of prototype arrays, we are challenged by a number of different defects. Each problem must be solved. It is a similar situation to the development of integrated circuits in the 1960s. New equipment must be built, and new materials and processes developed. R2R processing has some advantages and disadvantages for developing new processes. Experiments are cumbersome and can waste considerable material. However, some experiments such as varying the thickness of a film can be carried out very efficiently by simply varying the web speed.
A huge advantage for R2R processing is that the capacity of the research tools is sufficient for pilot production. So once a stable process is developed, scaling to manufacturing volumes is relatively straightforward. Our first target will be amorphous-silicon (a-Si) backplanes for electrophoretic displays because of the simplicity of the structure and modest thin-film transistor (TFT) requirements.
TC: Where do you stand and where do you need to be in terms of such process parameters as film/coating thickness and uniformity, contamination, defectivity, yield, surface roughness, reliability/lifetimes, drive voltages, field effect mobility, etc.?
CT: Since we haven't demonstrated a completely R2R-processed display, it is safe to say we are not there yet. There are no fundamental issues, just control of the defects. The device performance is equivalent to a-Si TFTs made with other processes. We have worked with Sigurd Wagner of Princeton to evaluate the effects of mechanical strain on device performance and found that devices continue to function after 50,000 tensile bend cycles around a 3-mm radius rod.
TC: In terms of defectivity, what are examples of more "generic" type defects and defects that are very process-specific to the line (e.g., shunt defects), especially those whose source mechanism can be traced back to deposition and coating processes?
CT: As mentioned before shunts are a big problem, but so were they for a-Si on glass 15 years ago. The SAIL process is new and has a very unique set of materials. We spent several years developing materials which could be used for several thousand impressions without degradation, which is necessary for printing a 1-km web. Currently, point defects in the creation of the stamp are a big focus since these defects replicate with every impression.
TC: Where would you like to see improvements in the materials and equipment sets, with special attention to the coating and deposition-related materials tools, and the supply chain infrastructure in general?
CT: Many companies are starting to develop wet and dry coating equipment for the R2R environment. The primary driver for this is the burgeoning solar cell industry. This is helping to bootstrap the flexible display industry. Much of the equipment for the SAIL process is custom designed and built in-house so we are not getting much leverage from this. Improved substrates are another important area. Device-grade PEN and transparent polyimide are exciting new substrate options.
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