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Home arrow Materials & Gases arrow Edition 36 arrow 36th Edition: High-k metal gate materials and processes for 32nm technology
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36th Edition: High-k metal gate materials and processes for 32nm technology Print E-mail
Apr 07, 2008 at 02:58 PM

C. S. Park, G. Bersuker, S. C. Song, P. Kirsch & B. H. Lee, SEMATECH, Austin, Texas; R. Jammy, IBM assignee to SEMATECH

ABSTRACT

This paper describes recent progress in high-k/metal gate stacks required for MOSFET scaling to the 32nm technology node. Band-edge metals for n- and p-MOSFETs have been developed through effective work function (WF) tuning, achieved by optimized doping of the high-k gate stacks. The mechanism of the EWF tuning is the dipole formation at the interface of the high-k dielectric and SiO2 interfacial layer. Possible solutions to the flatband voltage (Vfb) roll-off issue were obtained, an issue that presents the most significant challenge to achieving low pMOSFET threshold voltage (|Vt|) at low EOTs. The gate-first high-k/metal gated n- and pMOSFETs with low |Vt| and low EOT suitable for 32nm technology node applications have been successfully demonstrated.

36th Edition: High-k metal gate materials and processes for 32nm technology
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