"Our design flow can take designs started at 45nm and target it toward the advantages of 40nm," said John Wei, Senior Director of Advanced Technology Marketing at TSMC. "A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives."

TSMC said that the transition from 45nm to 40nm low power technology reduces power scaling by up to 15 percent. The processes are a direct shrink of TSMC’s 45nm offering, which includes low-k dielectrics, strain engineering and immersion lithography but not high-k and metal gates.