Advanced chipmakers have a dilemma: To pattern 32-nm half-pitch devices (let alone those 22-nm itty bitties), plain-wrap, single-exposure ArF immersion lithography doesn't have the legs to get it done.
EUV litho won't be ready in time, and although high-index liquids might be available, they won't do much good without their sibling high-index lens materials, which have orders of magnitude improvements needed before they prove their worthiness and become the glass of choice for high-end scanner lenses.
Don't worry, the Moore's Law scaling roadmap is not coming to a screeching halt just yet. A variety of double-patterning (DP) approaches using the exisiting ArF toolset offer a solution path for getting things done at 32 nm and reducing the k1 value without tweaking the lens' numerical aperture or exposure wavelength---and may even be extendable into the 2x-nm domain. Although they are workable, the two main schemes---double litho, double etch DP (LELE, for litho-etch-litho-etch) and sidewall spacer-defined DP (SDDP)---add process steps to the patterning sequence, which increases the cost and slows the throughput, thus diminishing their attractiveness.
Kurt Ronse, IMEC's lithography director, explained the dilemma during our meeting at the recent SPIE Advanced Litho show. The bulk of the Belgian consortium's work is focused on double patterning these days, he said, including materials-enabled alternative approaches that may eliminate the intermediate etch step for LELE or the extra process steps for SDDP.
Mireille Maenhoudt et al.'s paper detailed IMEC's work with several suppliers on these new materials, including one that will chemically "freeze" or harden the first round of resist patterning, "allowing the printing of two resist images on top of one another" without any damage to the first patterns. This alternative process flow has become known as "litho-process-litho-etch" (LPLE), with the "process" step synonymous with a freezing step that takes place in the litho track tool.
As Ronse pointed out, this approach could make fab logistics easier, since the FOUP stays on the litho cluster through the whole sequence, instead of being yanked out for additional etch process steps and then returning for the next patterning round. Since the wafer can be kept in the track tool, "it could provide a transparent process flow to the operators," he said.
The IMEC study looked at several alternative process schemes (including dual-tone developer and thermal cure resist), but the most promising one turns out to be JSRMicro's FZX F103 freezing agent. Demonstrations have shown definite advantages to adding the freeze step in terms of depth of focus, process windows (it was shown to be "within practical levels for adoption...in commercial 32 nm half pitch"), critical dimension variation and uniformity (CDU), and contact-hole formation.
Of course, the IMEC team concludes that further optimization and collaborative materials development efforts are needed, since there's room for improvement in CDU, line-edge roughness, overlay, defectivity, etch performance, and other areas. In order to minimize CD variation, the temperature and duration of the "freeze bake" step (admittedly a somewhat confusing juxtaposition of terms) has to be dialed in more, for example.
Still, the concepts have been proven with the printing of 32-nm dense lines, the freezing agent has shown surprising maturity for its young age, and the authors believe that "LPLE has the possibility to outperform LELE." In order to determine whether the process flow is indeed robust enough for manufacturing, Ronse cautioned that they "still need to run at higher volumes, to check control results from batch to batch, day to day, and week to week." This means IMEC needs more freezing material, which has so far only been provided in small quantities.
To hear JSRMicro's side of the story, I sent some questions via email to the one of the company's technical experts, Mark Slezak. Here are the edited Q's and A's of our interview.
Could you summarize the problems/challenges (extending DP, etc.) that led to the invention of the new material solution, FZX F103, AKA the freezing agent?
Leading IC manufactures have challenged materials suppliers to improve the overall cost of ownership associated with double patterning. One of the ways of accomplishing this is to offer an all in-track, single-etch solution, which is what led to the development/invention of JSR's FZX freezing materials.
What can you tell me about the chemical properties/composition of the material?
JSR's in-track freezing materials are based on a cross-linking technology that allows you to cross-link the first resist postfreeze and therefore avoid issues with secondary exposure or intermixing during the processing of the second resist.
Who leads the efforts in developing the material--whose idea was it for this kind of approach?
JSR has listened to our customers needs: they have clearly stated that a double etch solution is not a cost-effective solution. Additionally, many of the other technologies such as spacer technology involve deposition tools that also contribute to throughput issues. Therefore, it was our objective to develop an all-in-track solution that would enable double exposure, single etch, which significantly helps reduce the overall cost of ownership.
Could you describe how the material is used in the process (dual-line litho-process-litho-etch), and what benefits it provides?
Our FZX freezing materials are used in-line with a process flow that allows for a minimal throughput hit: to start, you coat, then expose the first resist; next, you freeze the first resist by applying our FZX materials, which requires a coat/bake/develop step; and finally, you do another coat step, then expose the second resist.
How well does the track tool handle the material? Are there any other tool-related or tool vs. materials issues to resolve?
No real track-related issues. The FZX material is cast in an alcohol-based solvent in order to avoid any intermixing with the ArF resists used today (similar to immersion topcoats). This often requires users to designate a coat bowl for the freeze material or using the same coat bowl as their immersion topcoat---by designating a coat bowl, you do not have to worry about solvent incompatibilities between the photoresist and the freeze materials.
What are the key next steps in developing the material? What "bugs" need to be worked out?
Many aspects of freezing for double patterning are being studied. We have shown that many factors such as CDU, MEEF, LWR, etc. are not effected dramatically by the freeze process, which means, what goes into the freeze process is what comes out. This puts pressure on us to continue to improve ArF photoresists overall. Additionally, we continue to optimize freeze materials to minimize any CD growth we may see postfreeze.
What are some examples of, and the status of, the latest optimization and materials development work at IMEC?
IMEC continues to be an excellent development partner and recently has helped us demonstrate the postetch feasibility utilizing freezing materials for double-patterning solutions for both memory and logic applications. We have sampled these materials to many leading-edge development centers (such as IMEC) and IC manufacturers, which are running our materials in a development mode. (Blogger's note:A JSRMicro team also presented a paper on the resist freezing process at this year's SPIE conference.)
Along those same lines, what are the key challenges that need to be worked out to make the freezing agent ready for volume production?
JSR continues to work with our customer base to understand what key issues need to be addressed, such as alignment, etch, and overall lithography improvements that are needed for double patterning.
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