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IMEC and JSR simplify double patterning steps
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IMEC and JSR Corporation have collaborated on using only one etch step
to reduce the cost of double patterning. 32nm lines and spaces were
printed with a double exposure/single etch process, effectively
freezing the resist after the first exposure. The freezing of the
resist after the first exposure prevents the resist from expanding or
shrinking, maintaining good CD control. When the second resist layer is
added, the two do not interact.
This technique allowed printing 32nm dense lines using dipole
illumination at 1.0NA. CDU for the 44nm HP lines was excellent (3s =
2.4nm).
IMEC said it was transferring the new process to its
1.35 NA immersion scanner from ASML (XT:1900i) to explore this solution
for sub-32nm half pitches (towards 22nm node).
Process steps for double pattering with resist freezing
Left: 32nm node 2D logic cells after litho-freezing-litho-etch. The lines from the two layers are perfectly merged on the stitching points. Right: The same cell patterned with litho-etch-litho-etch. The oxide hard mask has not been removed to show the lines obtained with the first litho step.