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Techcet chimes in on what's driving the changes in advanced interconnect materials |
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Mar 05, 2008 at 08:30 AM |
While the front end of line, lithography, and process integration areas often get the lion's share of attention in the advanced semiconductor manufacturing community, the back end of line presents its own prickly challenges and potential for bottlenecking.
The new edition of the ITRS lists three grand challenges associated with the interconnect realm: In the near term (through 2015, or up to but not including 22 nm), new materials will be needed to meet the specs for both high conductivity and low dielectric permittivity and the structures, processes, and aforementioned new materials must be engineered to be manufacturable.
In the long term (2016 and beyond, at or below 22 nm), the elephant in the BEOL room will be the transition from traditional scaling to equivalent scaling and functional diversity through the use of three-dimensional structures (i.e., through-silicon vias) and other nonconventional approaches (optical interconnects, carbon nanotubes, nanowires, quantum dots).
A common theme among all three grand challenges is the need for new, improved materials sets (in some cases involving radical changes), which can enhance performance and power in a cost-effective, manufacturable way without sacrificing reliability.
A just-published report from the Techcet Group, "Advanced Interconnect Materials for 65 nm through 32 nm," takes an in-depth look at both the technologies and markets in what the firm sees as the highest-growth-rate piece of the semiconductor process materials pie. Marketwise, the group forecasts the interconnect metals sector to grow from about $75 million-$80 million in 2007 to more than $100 million in 2008, hitting at least $275 million by 2013. The CVD low-k dielectric precursors segment topped $100 million last year and is expected to reach close to $150 million in 2008 and exceed $300 million by 2013. The biggest pie slice remains CMP slurries, which will close in on the $1 billion mark this year, with a fairly even split between copper and noncopper applications. The universal adoption of copper interconnect on logic and especially DRAM 4x-nm production lines is a big reason for Techcet's bullish projections.
I sought out the principals at Techcet to shed a little more light on some of the findings and forecasts in the new report. Acting as the group's spokesperson, Steve Holland, veteran of BEOL battles going back to his days at IBM in the early '80s and a managing partner at the consultancy, has provided Chip Shots (via email) with an overview on what's driving the changes in interconnect from 90 nm to 32 nm, with a few comments on 22 nm for good measure.
I asked Steve about some of the key interconnect lessons learned from previous technology transitions. "The move from aluminum-copper to copper damascene was hard work, for both IDM and OEM development, and it took years to optimize the process to get acceptable yield---and this was even without low-k [dielectric materials]. At the 130-nm node, the first companies to implement Cu had yields of <50% and were going crazy. The yields are now typically better than 90% in manufacturing.
"The first foray into low k with copper was pursued by IBM using a spin-on solution. In spite of top-notch teams at both IBM and the materials vendor, the effort failed at test. This was a highly followed lesson to the industry: beware of the issues that you don't know that you don't know."
As for how long copper can be used, Steve notes that "modeling tells us that Cu as a metal interconnect is not extendable for ever. Since carbon nanotubes aren't ready, expect a continuation of more and more Cu layers as a method of dealing with higher resistance Cu lines. The lessons from [the IBM spin-on experience] warn against venturing down the path of a major redesign of the interconnect technology.
"Also, interconnect resistivity is not sufficiently low; so to stay with Cu, we must develop a methodology for lowering the effective resistivity (see comments on barriers below). It is believed that the small geometries have small copper grain sizes compared to the bulk, and with more grain boundaries, you get higher resistivity.
"Reliability (particularly as a function of electromigration) is insufficient at smaller line dimensions," he continues. "This is always the greatest issue at geometric locations of current crowding; one example is at vias. Caps on the copper can improve Cu electromigration."
And what does Steve think about those barriers? "The barrier films deposited prior to copper deposition play a major role in both of the issues noted above. In the case of resistivity, a thinner barrier will allow a larger percentage of the total available linewidth to be in Cu, thus potentially lowering the effective resistivity. An ideal barrier will inhibit (or slow) electromigration, leading to superior reliability.
"Examples of films in evaluation include PVD copper manganese, which is expected at 32 nm but not before. Copper manganese is relatively easy to deposit and form as a barrier and offers some additional benefits that are discussed below. Copper can be electroplated directly on this film. Ruthenium has also been considered, as one can electroplate Cu directly on it as well, but there seem to be some problems with [this material]."
When it comes to capping layers, Steve and his colleagues believe that an ideal layer "would primarily inhibit the oxidation of copper, [since] even surface oxidation impacts the line resistance. But it would also not interfere with the line-to-line (i.e., via) resistance. Finally, it would improve the electromigration resistance of the Cu interconnect, while not driving up the resistance-capacitance (RC) delay characteristics of the circuit.
"Here are some examples of the film genealogy. Silicon nitride has been used as a cap at 90 nm or larger, but it has a rather high dielectric constant of about 7, negatively impacting the effective capacitance and thus the RC delay. At 65 nm, a silicon carbide nitride film is preferred with a dielectric constant of about 5. Clearly an improvement, but more is needed. Future capping barriers may be copper silicon nitride (formed by reacting the Cu after CMP with SH4 and NH3) or cobalt tungsten phosphide. Expect CuSiN at 32 nm."
What about the dielectrics front? "Dielectric technology has been 'behind the eight ball' since the roadmap was first created in the early 1990s," Steve notes. "The published goal for the dielectric constant to meet performance requirements has never been met in 16 years. That's one reason that some logic products have resorted to using up to 16 levels of metal, in order to achieve adequate interconnect performance---and at a very expensive price.
"There are numerous schemes that are in development or discussion on how to get the effective dielectric constant back on track. One prominent plan is a hybrid process that uses a very low-k spin-on (yeah, spin-on again) material in combination with a material known to have more stable properties that will facilitate integration. Certainly there are still groups working with porous low-k CVD films and porous low-k spin-on films to achieve the goals, but the IBM experience referred to above is always haunting. This will work at 45 nm and may work at 32 nm, if the IDM agrees to a k value of >2.
"Air gaps have been demonstrated and appear feasible in both lab and manufacturing environments. There is some belief that in order for the industry to achieve a K-eff of <2.0, only air gaps are feasible because the integration challenges of the other low-k materials are just too great. When will air gaps happen? [I see] 22 nm as likely for the wider industry, [although] some leading-edge groups may do this at 32 nm, if they desire a k of <2 (which is the roadmap at 32 nm)."
Gone are the days of neglecting plugs and vias, according to Steve. "With the primary focus on the interconnect metallurgy and the dielectrics (due largely to the well-known RC delay issues), plugs and vias have tended to be overlooked. Not any more. Plugs and vias play critical roles in both the effective interconnect resistance and also in the electromigration resistance. (By the way, the word resistance is used twice in the previous sentence: interconnect [or wiring] resistance is bad, while electromigration resistance is good!)
"Plugs fill the contact holes between the device poly and the first level of metal. This plug metal has been tungsten since IBM developed Cu damascene in the late 1980s. Now being examined are copper and rhodium, which have lower resistivity than tungsten.
"Vias connect different levels of metal to each other," he continues. "Ideally, vias would be the same metallurgy as the interconnect lines (i.e., Cu), but without any resistance increasing barrier metallurgy between the films. At 90 nm, there was a tantalum/tantalum-nitride barrier film in the bottom of the via adding resistance to current flow through the via. If CuMn (discussed earlier) is used as a barrier film for metal deposition, some of the manganese will diffuse to the surface of the copper during metal anneal and will then be removed during the CMP step. This would result in lower via resistance, since the end result would be a Cu-to-Cu connection in the interface of the via."
For info on obtaining the advanced interconnect report or contacting Steve or one of the other Techcetters, click here.
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