Mike Lercel, director of Sematech's lithography efforts, couldn't tell me about the news of the consortium's purchase of Molecular Imprints' new, improved Imprio 300 step-und-flash imprint litho system and planned delivery to Albany this summer when I spoke with him Monday---but he would have liked to.
The deal wasn't finalized from the Sematech side until midday Tuesday, with several details and signoffs finally coming together coincidently during the SPIE event's frenetic, relentless technological and commercial energy.
When I ran into Mike during the JSRMicro evening reception, I gently busted him for not sharing the news with me. He explained that he was under strict orders not to utter a peep, so he couldn't tell me about it during our meeting the day before, even on a confidential basis. This is the kind of hard embargo that those of us in the industry media don't particularly like, but we have to deal with sometimes as a part of doing business. (What's the matter, don't you trust us?)
The acquisition of MII's latest tool by Sematech marks a turning point in the evolution of nanoimprint lithography from intriguing but "impractical" next-gen approach into a potentially viable candidate for production at the 32-nm tech node and beyond. Although powerful companies like Toshiba, Samsung, IBM, Hitachi, Seagate, HP, and others have publicly presented data from their work using NIL in unit-process development, prototyping, and template fabrication in the IC and high-density memory storage arenas, the major consortia like IMEC and Sematech have given little or no love to imprint---until now.
This year's SPIE Advanced Litho extravaganza features three sessions' worth of nanoimprint presentations, plus elements of the technology scattered among papers dealing with e-beam direct write and other topics. Toshiba's results showed MII's NIL tool/process achieving template resolutions down to 22-nm dense patterns, images that prompted presenter Ikuo Yaneda to say, "these are very, very beautiful pictures, I think."
Of course, pretty pictures are one thing, but CD uniformity, line-edge roughness, overlay accuracy, and defectivity are another ball of wax. But in all those key areas, Toshiba has found NIL comparable with optical litho, or at least within engineering striking distance---and exceeding current EUVL stats. Yes, defect density has to be reduced without a loss in throughput, the etch selectivity needs to be higher, and the equipment, resist, and template/mask parts of the infrastructure have room for improvement, but Toshiba believes strongly in the extendability of NIL for a variety of test structures--and perhaps beyond.
On the hard-disk side, Seagate's fast-talkin' Xiao-Min Yang talked about the various challenges in e-beam litho in order to fabricate the templates that will be needed for terabit-scale bit-patterned media. But EB direct writing alone won't be sufficient to make those templates---a combination of UV-cure NIL and electron-beam tech will "probably be the only way to go for manufacturing," because of the resolution, throughput, and cost requirements involved (although many small-dot patterning process development challenges remain).
MII's John Doering told me one of NIL's key battles is the perception issue, not only that of proving his company's S-FIL technology is the best suited for manufacturing, a veritable "drop-in replacement" for optical litho in a mix-and-match process scenario, one which can hit the requisite overlay targets and uses standard mask, resist and related processes of record. But the even bigger perceptual struggle remains NIL's general validation and acceptance in the lithographic and chipmaking communities.
Certainly, the fact that customers are coming out and sharing their NIL data and results has helped this learning process along, but many very bright, committed, but optically obsessed lithographers still either poo-poo or at least express reticence about imprint's eventual success as a high-volume manufacturing solution.
With Sematech's purchase of MII's system and its pending installation at the Albany Nanotech complex, NIL's manufacturability will be put to the test in the kind of collaborative industry environment that will demonstrate if the tech will be ready for CMOS (and post-CMOS?) prime-time in the ever-shrinking half-pitch generational flow. Along with the companies doing their own NIL due diligence, the consortium's efforts will help determine if today's high-resolution and image fidelity prototying capabilities will one day evolve into imprint litho proving its mettle as a cost-effective, production-worthy alternative to more costly and complex approaches.
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Comment by GUEST on 2008-03-03 14:27:36
Process bias cannot exceed minimum printed pitch. In the case of double patterning, the minimum printed pitch is 2x the actual target pitch. So indeed the process bias is very helpful to filter out a larger number of defects.
The larger features of double patterning are also less sensitive to the proximity of non-printing defects as well. | Comment by GUEST on 2008-03-03 11:14:15
This is a nice discussion on defects. But the issue is actually tied up into the whole process integration. For example, if you had a mask whose target is to print 60nm contact holes, which are subsequently shrunk by reflow process to 10nm, even if you have 50nm initially printable pinholes on the mask, they will not survive the reflow. It is because the process bias is -50nm. A zero bias assumption is too naive in many cases.
So the issue is not really what defect can print, but what defect will come out of the process.
The mask defects that you need to worry about instead are those which cannot be detected or printed but still influence the main primary feature printing because of their proximity. That is a big deal. | Comment by GUEST on 2008-02-27 15:18:16
A 100 nm mask defect on an NIL mask will print as 100 nm on the wafer. A 100 nm mask defect on an EUV mask will print as 25 nm on the wafer with 4x reduction. A 100 nm mask defect on an ArF immersion mask will not print as 25 nm on the wafer with 4x reduction, because the defect cannot be resolved even with 1.35 NA. | Comment by GUEST on 2008-02-29 09:35:09
Defects are always bad, I agree. But imprint lithography is working today. You can't really say that about EUV lithography. There are over 100 facilities performing imprint lithography today... how many facilities are performing EUV? 5?
SPIE marks the end of EUV and the rise of imprint. Look at the results. base your judgement on the data. | Comment by julian1959 on 2008-02-29 09:35:36
The comment about defect is correct so some work will need to be done, BUT a great benefit that seems to get lost in the shuffle is that Imprint will eliminate all that OPC and other RET technologies. You can see the RET/OPC guys poo pooing this too. The issues are plenty for any of the next gen litho tools, why not have Imprint in the arsenal as it appears to be the lowest cost if it works out. |
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