At Micron Technology’s analyst day last week, Mark Durcan, Micron’s President and COO, outlined the company’s low-cost manufacturing plan for both DRAM and NAND flash memory in 2008. 

In respect to NAND flash, Durcan highlighted that it expects to begin sampling of a sub-40nm device as early as the second quarter of 2008. Sub-40nm NAND production would start ramping in the second half of 2008.

Gartner’s market analyst Joseph Unsworth said in the research firm’s weekly newsletter that this device is believed to contain 35nm node features and would overtake Samsung's position as the No. 2 NAND cost leader and would rival Toshiba and SanDisk’s cost leadership sometime in 2009.

Durcan said at the analyst meeting, “…we believe that we have caught the industry leaders at the 50nm node and as we look to the future we expect [to be] accelerating away from them.”

Currently, Micron is predominantly in production with NAND at the 50nm node at 300mm fabs in Virginia and Lehi and expects to begin production at its IMFT joint venture fab in Singapore in the second half of 2008.

Durcan also noted that in respect to DRAM process technology, the company had virtually completed the transition to the 68nm node. Comparison between competitor nodes is not as relevant in respect to DRAM as with NAND, mainly due to Micron’s having a 55mm squared die at 68nm, that it claims is by far the smallest die in the industry.

Micron expects to start production of its 58nm node DRAM at its Manassas 300mm fab in the second half of 2008. Immersion lithography will be used at this node and beyond, Durcan said.

To emphasize the low-cost memory manufacturing strategy, Durcan noted that at the end of 2007, the company was fabricating 55 percent of its DRAM on 300mm wafers but this would reach approximately 75 percent by the end of 2008.