Dr. Liang Chen, General Manager, CMP Division, PPC Product Business Group, Applied Materials Inc, USA

ABSTRACT

Chemical mechanical planarization (CMP) has become a key enabling technology for semiconductor fabrication [1]. Conventional CMP uses slurry, a resilient polishing pad and down force on the wafer to planarize multiple device layers. This makes possible chips with >8 metal layers and 90nm features. New materials, such as copper (Cu) interconnect and low-k dielectric films, are replacing traditional Al and SiO2. These offer the lower RC delay values required to gain higher performance and continue progress on Moore's Law. Yet issues are developing for conventional CMP, especially with advanced 65nm devices, which can employ up to 11 metal layers. Continued device scaling, following Moore's Law, necessitates tighter planarization and process control range at each technology node to meet integration requirements. Additional dielectric polishing, called “overpolish,” could be used to gain better overall uniformity. Although this approach helps to meet the closer limits desired, it adds to the Cu loss and reduces the overall layer thickness. Furthermore, it might not be feasible for ultralow-k dielectrics that need to retain a protective capping layer.