M. Mellier, T. Berger, R. Duru, O. Hinsinger & G. Wyborn, STMicroelectronics, France; M. Rivoire, CEA–LETI, France & K-L. Chang, Y. Wang, V. Ripoche, S. Tsai & M. Thothadri, Applied Materials, USA

ABSTRACT

With the most advanced generation of integrated circuits using the integration of copper and fragile low-k or ultra low-k (ULK) dielectrics in Cu interconnects, the constraints on Cu chemical mechanical polishing (CMP) have become critical. There has been a great effort made to develop Cu CMP processes at lower pressures with improved topography behaviors to reduce sheet resistance (Rs) variations and to meet the stringent designs rules and compatibility with the lithography budget for depth of focus (DOF).