R. Arghavani, A. M. Noori, A. Gelatos, A. Khandelwal, S. Gandikota & S. Felch, Applied Materials, California, USA, & S. E. Thompson, University of Florida, USA

ABSTRACT

Significant breakthroughs in tool set, process and integration development have enabled implementing ~2 GPa of channel strain at the 45nm technology node.  High stress dielectrics (>2 GPa) are routinely used in several steps in the high-volume manufacturing process flows to introduce uniaxial compressive and tensile stress in the channel of MOSFETs.  The stress films are used for shallow trench isolation, contact etch stop, pre-metal dielectrics, removable films for stress memorization techniques, spacers and even salicidation.  Epitaxial silicon germanium in the source and drain (S/D) of p-MOSFETs is also adopted in high volume manufacturing resulting in a significant boost to p-channel performance.  Current innovative material processing appears to transfer enough stress to the channel to increase electron and hole mobility and meet 32nm and 22nm node logic performance goals.  However, there are significant signs that this improved mobility gain will not transfer into enhanced device performance due to parasitic external resistances becoming a bottleneck.  Such external resistances arise from junction, salicidation and contact processing.  Thus, a paradigm shift in device scaling is occurring at the 32nm technology node.  In this brief, we quantify the external resistance problem and offer possible solutions so that the full benefits of strain engineering are realized.