The timing of this year's Industry Strategy Symposium and the fiscal year-end earnings announcements from both ASML and Intel taking place during the same week may have been coincidental, but the news certainly opens up a few avenues for random (and not-so-random) numbers games---a favorite pastime here at Chip Shots.
Intel's 2007 revenues came in at a healthy $38.4 billion, which is nearly $3 billion more than Gartner Dataquest's total wafer-fab equipment (WFE) market number ($35.56 billion) for the same period.
By comparison, the Intel sales figure beats SEMI's estimate of the wafer-fab materials market for 2007 ($25.29 billion) by about $13 billion. How many other industries boast 800-pound gorillas with sales revenues greater than some of their entire critical supply-chain sectors?
One constant buzz at ISS focused on cutbacks in capital expenditures by chipmakers in 2008. Dataquest may be forecasting about a $7.8 billion drop (or -13.2% vs. 2007), but Intel says it will actually spend more this year. Its stated estimate of $5.2 billion (plus/minus $200 million) makes it one of only three semiconductor manufacturers (the others being Toshiba and IBM) that plan to increase capex this year, according to Dataquest's top 20 "big spenders" list. Intel's pop represents about a 8.3% increase over its 2007 spending, and 10.2% of total industry capex forecast for 2008 (vs. 8.1% of same during last year). Although Samsung still lays claim to el numero uno position for capex, the Korean company plans to spend 16.4% less in 2008 compared to last year, or $7 billion vs. $8.37 billion, according to Dataquest's data.
Intel's 2008 capex is only a few hundred million less than ASML's annual revenues for 2007, which hit a record high at 3.809 billion Euro ($5.561 billion, @ $1.46 per Euro). The Dutch litho company's sales equate to about 15.6% of Dataquest's total 2007 WFE market, and about 74% of the research firm's litho stepper/scanner segment estimate ($7.5 billion) for last year. (ASML own data show it holding about 65% revenue market share versus Nikon and Canon.) It's also interesting to note that ASML's gross is very close to the total revenues for the three main litho materials sectors combined---photomasks, photoresists, and resist ancillaries---which SEMI estimates will collectively tally $5.631 billion in 2007.
Average selling prices (ASPs) also prompted alot of discussion at ISS, but the emphasis was more on plummeting memory-chip prices rather than the going rates for new fab equipment. Bill McClean's chart of plummeting 512-Mb DDR2 DRAM prices over the course of 2007---from a January average of $6.20 to December's horrendous 95 cents---prompted the IC Insights president to exclaim, "they've got nowhere to go but up."
ASML is singing a different ASP tune entirely, although "up" is still an operative term. It announced 4Q07 per-new-system averages of 16.5 million Euro ($24.67 million), backlog new tool ASPs of 19.1 million Euro ($27.89 million), and 1Q08 new-system ASPs expected to be 18.9 million Euro ($27.6 million) for the vast majority of the 50 platforms scheduled to ship this quarter. The higher price points of the company's immersion scanners---expected to double in sales volume in 2008---are leading to, drumroll please, "significant ASP growth."
Speaking of those Twinscan XT:1900i immersion tools, ASML says it has shipped 20 of them since July 2007, including several to Japanese customers. It claims that "some of these systems are running consistently at over 2100 wafers per day." That translates into 87.5 wafers per hour per tool (sorry about that half-wafer), and about 766,500 wafers per year per tool, calculated on a pure (and admittedly crude) 24-hour/365-day basis.
Sounds impressive, but it falls short of the kind of productivity that the company touts in 24 of its silicon-schlepping "dry" scanners, which are said to have processed more than 1 million wafers per year per tool in certain customers' fabs. That rounds out to about 2740 wafers per tool per day and 114 wph, or 640 more wafers daily at a clip 26.5 wph faster than their best-performing "wet" cousins.
None of this back-of-the-envelope number crunching accounts for downtimes caused by maintenance, repair, failures, and the like, so the actual throughput numbers will undoubtedly be higher once the "real" uptime is calculated. Yet the evidence suggests that, for the time being, when a chipmaker purchases an immersion tool from ASML, it pays a higher ASP for lower productivity!
This does not weigh the process-enabling bump that such systems provide to those teetering on the bleeding edge. Also, this "less throughput bang for the buck" aberration will be short-lived, as the tool company helps its fab customers further dial in the immersion process, the lines ramp to high volumes, and the supplier and end-users get more experience with the systems in general, much as they have with dry 193-nm ArF scanners for several years.
But if those customers come from the DRAM and flash worlds---and 66% of ASML's stated backlog is destined for memory apps---there's some temporary loopiness afoot in a corner of the ASP realm.
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Comment by GUEST on 2008-01-19 13:29:13
Tom Cheyney, Chip Shots blogger, REPLIES: Actually, two of the standard metrics for measuring tool throughput (AKA productivity) and installed factory capacity are wafers-per-hour and wafer-starts-per-(fill in time element here). Of course, the number of functional chips per wafer is critical too (yup, that's the yield), but my point was to have a bit of eyebrow-raising, number-gaming fun with the ASML data, not to question their pricing model for what are very sophisticated pieces of process equipment, tools that enable the continued
progress of the Moore's Law paradigm. | Comment by GUEST on 2008-01-18 12:59:15
you completely miss the point here, chipmakers tend to make chips and not wafers, so their productivity should be calculated in units of chips, and not in units of wafers. knowing that immersion leads to more chips per wafer, you should redo your calculation. then you'll undersand that ASML has a very reasonable excuse to increase the price of their machines. |
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| Senior Technical Program Manager (Dublin, Ireland, 02/04/2008) | | Senior Embedded Design Support Engineer (Shannon, Co Clare, Ireland, 19/03/2008) | | Embedded Support Engineer (Intel Shannon, Co Clare, Ireland, 19/03/2008) | | Senior Component Design Engineer (Intel Shannon, Co Clare, Ireland, 19/03/2008) | | Product Marketing Manager/Engineer [Fresh graduates/entry level] (Milpitas, 01/09/2007) |
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