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Consequences of ITRS Roadmap Acceleration for Device Makers on Advanced Lithography Integration into
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PETER ZANDBERGEN, Philips Semiconductors, Kapeldreef, Leuven, Belgium
ABSTRACT
As the ITRS roadmap confirms its accelerated pace of two years
per technology node, the status and maturity of the lithography
solutions upon introduction of the nodes is influenced. Though on paper
the technological solutions on individual domains as mask, resist and
tools are ready just in time, integration into full process flowcharts,
however, is not thoroughly addressed. In this paper we will address the
impact of this shrinking time window on the focus areas going from
basic R&D of process step concepts down to release of the intended
solutions in process technology at product sampling. In the domain of
SOC manufacturing this also implies modifications in process solutions
that have to come after initial introduction of a technology. In
addition we indicate how we see that the global programs as executed in
various pre-competitive consortia by themselves not necessarily prepare
for a smooth integration of technologies such as 157 nm or EUV
lithography into manufacturing situations. We give some examples of
such less considered challenges that have to be addressed by device
makers to assure robust and proven manufacturing boundaries for the use
of these challenging lithography technologies.
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