Michael D. Archuletta, Chris Constantine & Dave Johnson, Unaxis Semiconductors, Florida, USA

ABSTRACT

Wafer dimensions continue to accelerate downward towards ever smaller features and the legendary Moore’s Law is still valid for current silicon devices. As wafer IC dimensions approach the physical limitations of silicon physics, the lithography techniques used to print these patterns on silicon become very difficult to perform. This article describes advances in this area down to 65-nm sizes.