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Dispatches from IEDM: Annealing method no flash-in-the-USJ-pan at sub-45-nm |
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Dec 13, 2007 at 01:29 PM |
One recurring front-end-of-line process theme from this week's IEDM was the critical importance of advanced, next-gen annealing in the ability to achieve the junction depth scaling needed for sub-45-nm technologies.
Not old-school, plain-wrap thermal annealing will do anymore: the new-fangled flash and laser varieties that will replace the apparently stalled spike technique (it pushes the junctions too deep) are capable of millisecond bursts of energy to (hopefully) get the job done in a high-k dielectric/metal gate (HKMG) stack.
In one interesting Session 13 presentation, Pankaj Kalra, a grad student from UC Berkeley, got the nod to discuss the findings of a team composed of researchers from Sematech's FEOL program, several consortium member companies, and scientists from Korea and the University of Texas on how flash annealing might affect various performance and reliability metrics on MOSFETs with hafnium silicon-oxide/titanium nitride HKMGs processed on a gate-first flow. The ultrashallow junctions (USJs) were formed using millisecond bursts on a Mattson flash-lamp anneal system in a four-part sequence: the wafers were bulk heated to an intermediate temperature between 650 and 800 degrees C, then flash heated to peak temps between 1200 and 1350 degrees C on the device side of the wafer, then cooled by thermal induction, and then cooled further in a radiative fashion.
The team measured sheet resistance both with contact and noncontact methods and found that the noncontact approach was the more appropriate one to get the proper measurements. (The contact method turned out to be inaccurate because the probe penetration causes a leakage error, noted Kalra.) They discovered that flash annealing reduces dopant diffusion but enhances dopant activation compared with spike anneals. With fabbed sub-100-nm gate length devices as their test vehicles, the researchers activated the implanted source/drain dopants with both spike and flash anneals, and then used a variety of analysis tools to investigate short-channel effect (SCE) control, gate-stack integrity, and mobility degradation and recovery.
What kind of results did they see? For the SCE tests, flash anneal beat spike, providing shallower junction depth and improved SCE control (as in better subthreshold slope and lower drain-induced barrier lowering, or DIBL [a new initialism, rhyming with "tribble," for the ever-growing Chip Shots unofficial glossary]. As for the gate-stack physical analyses, there was no frequency dispersion or hysteresis seen, and gate leakages were on par with historical HKMG trends. Findings on bulk charge trapping---an HK reliability/performance bugaboo---showed negligible positive-bias temperature instability variation between the two annealing techniques, although the flash-processed stacks had a higher time-zero breakdown voltage than the spike-treated ones---a still-not-understood, possibly high-k crystalline structure-related behavior that is the focus of ongoing study.
On the electron mobility front, things were a bit dicier. Both the peak and high-field mobility values were found to be degraded for a flash-annealed stack, so the team fired up the charge-pumping measurement tools to find out why. Seems the cause of the mobility loss was a higher interface state density, which was evidently consistent with degraded negative-bias temperature instability seen in other analyses. Further tests showed a big change in wafer radius of curvature, possibly caused by not-completely-unexpected wafer-level stress buildup after the flash anneal. There were also indications of a higher density of high-k induced oxygen trap or oxygen vacancy defects within the silicon-oxide interfacial layers.
But those tricky carrier mobility values can be brought back into line through the use of an optimized postmetallization anneal (PMA) process, according to the team's findings. This added step seems to reduce the interface-trap density (as seen in lower subthreshold slope values), and PMA can be more tightly dialed-in to further improve device characteristics.
Although the laser-thermal annealing crowd might disagree, flash anneal seems to have some technical appeal as a method for USJ creation, including reasonable compatibility with HKMG stacks. But as Sematech manager Prashant Majhi told me after the presentation, whether flash, laser, or a combination of the two techniques eventually perseveres as the process of record remains an open question. What is not in question is that the discussion will continue to be a hot one (pun intended) in 2008 among aficionados of advanced transistor formation.
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