IMEC is reporting in a paper today at the IEDM Conference that work undertaken closely with partners NXP and TSMC in particular could offer a simpler, less complex and less costly integration scheme for high-k dielectrics and metal gates at the 32nm node and a possible candidate for FinFETs for the 22nm node and below. 

A major challenge in using high-k dielectrics for CMOS devices is the high threshold voltage resulting in low performance. Dual metal gates in combination with dual dielectrics can solve this problem but have the drawback that extra processing steps are required, resulting in a higher processing cost.

IMEC claims significant progress in improving the performance of planar CMOS using hafnium-based high-k dielectrics and tantalum-carbide metal gates. Low threshold voltage (V_t) is achieved by applying a thin dielectric cap between the gate dielectric and metal gate. The use of laser annealing for gate stack engineering resulted in a significant reduction of the minimum sustainable gate length and improved short-channel effect control, according to the paper.

Both a lanthanium- (La₂O₃) and dysprosium-based (Dy₂O₃) capping layer was used for nMOS and an aluminum-based capping layer for pMOS. Symmetric low V_t of +/-0.25V were achieved and drive currents of 1035µA/µm and 505µA/µm for nMOS and pMOS respectively at V_DD of 1.1V and I_off of 100nA/µm. Successful CMOS integration was illustrated by a ring oscillator delay of less than 15ps.

IMEC developed a simpler, lower-cost integration scheme using only one dielectric stack and one metal. A thin dielectric cap being deposited between the gate dielectric and metal gate which effectively modulates the work function towards the optimal operating zone.

The use of laser anneal instead of spike anneal (RTP) is applied to reduce the effective oxide thickness. Using laser-only annealing higher activated and shallow junctions could be achieved.

Picture 1. Ring oscillator realized with hafnium-based high-k dielectrics and tantalum-carbide metal gates targeting the 32nm CMOS node.

Picture 2.  I_on/I_off performance for high-k/metal gate CMOS

Picture 3. Ring oscillator performance realized in high-k/metal gate CMOS