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 IBM has said that its alliance members that include AMD, Chartered Semiconductor, Freescale, Infineon, and Samsung will have its 32nm process ready for use using high-k gate-first approach in the second half of 2009.
"IBM's alliances have demonstrated the 'high-k gate-first' approach in a manufacturing environment, an achievement that provides clients with a simple, scalable pathway to incorporating the high k material innovation in semiconductor development without introducing additional design complexity," said Gary Patton, Vice President, IBM's Semiconductor Research and Development Center on behalf of IBM's technology alliances. "This industry leading development comes from leveraging the collective engineering talent and breadth of market experience across the six Alliance Partner companies, as well as world-class R&D facilities such as UAlbany NanoCollege's Albany NanoTech complex, in order to maintain an aggressive road map."
Using SOI wafers, IBM claims that in microprocessors the high-k/metal gate process enables up to a 30 percent performance improvement or a 45 percent reduction in power usage.
IBM and its Alliance Partners have also developed a 32nm low-power foundry CMOS process using the 'high-k gate-first' approach that has been demonstrated in an SRAM configuration.
From right to left: Craig Lage, Project Leader, Freescale; An Steegen, Project Manager, 32nm Bulk Technology, IBM (sitting, left); John Pellerin, Project Leader, AMD; Ja-Hum Ku, Project Leader, Samsung; John Sudijono, Project Leader, Chartered (sitting, middle); Mukesh Khare, Project Manager, High-K/Metal Gate Technology, IBM; Richard Lindsay, Project Leader, Infineon; Effendi Leobandung, Project Manager, 32nm SOI Technology, IBM (sitting, right).
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Comment by GUEST on 2007-12-11 09:32:01
The title should say "IBM alliance members to have 32nm high-k/metal gate process in 2H09" iso "2H07"... | Comment by GUEST on 2007-12-11 09:44:43
Editor Response: Apology given, we made a mistake it is indeed 2H09 and missed our pre-publishing checks. | Comment by GUEST on 2007-12-11 10:47:20
Editor Response: We would expect that if immersion lithography is to be used at the 32nm node and without higher index fluids than water being qualified by then, then double patterning would be used. | Comment by GUEST on 2007-12-11 09:46:54
Does this process use liquid immersion tools? |
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