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TEL participates in SEMATECH’s 3D interconnect program |
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Nov 08, 2007 at 06:05 PM |
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 Tokyo Electron has joined SEMATECH’s 3D Interconnect Program, the goal of which is to enable high-volume manufacturing of 3D-TSV (through silicon via) chips by its members in a cost-efficient way.
“3D integration will become an indispensable technology in the near future, as device scaling becomes more and more difficult and as end products in electronics become more diversified,” said Masayuki Tomoyasu, Senior Vice President of TEL Technology Center, America, LLC. “SEMATECH’s 3D Interconnect Program has broadly surveyed the industry to understand technical and economic requirements and has gathered technological knowledge to realize those requirements. SEMATECH provides the most suitable development foundation for TEL to apply our current wafer process knowledge to 3D-TSV processes. Together we will contribute to industry-wide implementation of 3D.”
Prior to joining the 3D initiative, TEL was engaged with SEMATECH in a joint development program to address early development challenges in 3D-TSV, including deep-silicon reactive ion etching (RIE), cost modeling, process benchmarking, standards development, and technology roadmapping.
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