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Rejuvenation of CMOS key to nanochip development, says ASMC keynoter |
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May 23, 2006 at 07:47 AM |
The chipmaking industry must rejuvenate CMOS with new technologies, not replace the time-tested approach with biological or quantum computing models, espoused UC Berkeley prof Chenming Hu in his keynote today at ASMC here in Boston.
Hu said a continuous evolution, not revolutionary changes, will drive the extension of CMOS to the nanoCMOS realm. Advances in insulation materials, device structure shapes, semiconducting materials, transistor mechanisms, and lithography can all help CMOS (albeit in some mutant forms), continue as the basic IC platform.
Hu ran through a variety of options and possibilities for scaling and advancing CMOS for many years to come. On the insulator side, he pointed to the use of high-k dielectrics. Mobility scaling could benefit from the use of high-mobility germanium thin films on a silicon substrate, which would not require new equipment or fab infrastructure. He also encouraged examination of other compound semi materials or even carbon nanotubes to tweak electron mobility. Perhaps double-gate transistors or FinFET-type device structures offer a way to extend CMOS, Hu noted (although he poo-pooed the likelihood of 3-D processors, but championed their use for memory). More exotic approaches such as template-directed self assembly were among his evolutionary CMOS scenarios. The integration of MEMS and CMOS is already on the table and quite realistic.
"The ingenuity of engineers cannot be overestimated," he said, adding later, "the success of the semiconductor industry can be stated in one word--incrementalism." For Hu's vision of aggressively incremental CMOS to take place, it will take a massive amount of innovation and ingenuity, but nothing that seems beyond possibility. The alternatives to evolved CMOS amount to the kind of profound paradigm shift that might just be too costly and difficult to achieve, especially in the next decade or so.
I was left with a lingering question: how can you do DFM (design for manufacturing) for some of these souped-up CMOS chips if you don't know how to design or manufacture them? As one attendee quipped, DFM can mean "design for monkey-business." If anyone in the DFM community can shed light on any preparations and capabilities in place or coming soon that could handle the design and handoff to manufacturing of these novel devices, please comment.
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