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Development efficiency source of competitive edge, says ISMI keynoter Inoue |
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Oct 10, 2006 at 12:13 PM |
One key to competing successfully in digital consumer electronics is efficient development practices, said Michihiro Inoue in his keynote at the ISMI Symposium in Austin earlier today.
The Matshushita exec provided details of his company's improved business model, a model that depends on the introduction of leading-edge, advanced semiconductor processes ahead of the competition and the acceleration of various phases of R&D and production ramps.
This recipe for success banks on four elements, according to Inoue: collaborating to reduce process development times, employing an integrated platform to enhance LSI development effectiveness, using vertical integration to shorten startup times for volume production, and establishing advanced process control technology along with an "intelligent" fault detection classification/design for manufacturing (FDC/DFM) database to help control variances.
Inoue offered specific examples of each element in the model, pointing to examples such as Matshushita (AKA Panasonic) alliances with IMEC, Renesas, and ISMI and FDC-optimized maintenance cycles and reduced use of monitor wafers. Other improvements in fab-ramping practices included a faster utility supply hookup method and a quicker way to start up the chemical supply systems.
The proof in the pudding came when Inoue proudly noted that his company's crown-jewel fab, Uozo E, came on line--from groundbreaking to volume production--in a record-breaking 17 months. He also claimed that Matshushita was the first to hit volume at 65 nm and the first to get to market with a 65-nm consumer-oriented chip, when the device came out in Q405.
He also revealed some information about the parameters and specs of the 65 nm process, as well as the company's roadmap for 45- and 32-nm generations. The lithography plan calls for ArF immersion with an NA of 1.2 at the 45-nm node and immersion with double patterning with an NA of 1.35 for the 32-nm process. Increasing use of strain, sSOI, <3.0 low-k dielectrics, ALD barriers, air gaps, the continued use of copper interconnect, and eventually high-k gates are among the other roadmap details.
I do need some help in translating some peculiar corpo-speak that Inoue used during a description of Matshushita's business models and strategies, though. Can someone tell me what it means to "accelerate the oligopoly by black-boxing the core technology"? Is this another way of saying they will "leverage their core competencies for global domination"? Maybe I should just work on achieving critical mass.
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