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KLA-Tencor lays claim to the wafer's edge |
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Nov 07, 2006 at 05:17 PM |
In my Oct.
26 post "Life on the (wafer's) edge just got better," I mentioned KLA-Tencor's new VisEdge CV300 inspection tool. During a visit to Silicon Valley last week, I received an in-depth briefing on the new system from K-T's Srini Vedula.
With studies showing that better edge yields and fewer edge-related surface defects could result in a potential multimillion-dollar revenue pop in a high-volume 300-mm fab, this is not a "same ol' same ol'" product-technology introduction. Vedula said that he has seen serious work internally at the fabs on wafer-edge engineering and edge yield in general, so interest is running high. Talk about a classic "return on investment" scenario!
He cited a growing frustration in the fab community over the lack of production-worthy edge-inspection tools, systems that could be used in the actual manufacturing environment. K-T's new platform, which features the proven multisensor optical surface analyzer (OSA) technology developed by its Candela business unit, has a decade-long track record in thin-film-head and compound semiconductor fabs.
One key advantage, K-T believes, is the CV300's ability to inspect all five edge regions, from the top near edge, to the top bevel, all the way around the apex to the bottom bevel and bottom near edge. Different processes cause or impact different defects of interest (DOIs) in the various "zones," many of which are difficult or impossible to detect with existing inspection technology. This is especially true given increased device complexities, knotty materials and process integration issues, new processes (e.g., immersion lithography), and ever-more-fragile layers. Delamination and residue top the list of problem defects, with particles, cracks, and chips also troublesome.
Top-bevel blister undergoing delamination. (Photo courtesy of KLA-Tencor)
The compact K-T platform not only inspects and detects defects but classifies and sources them as well, sending the information into the company's Klarity yield management system to correlate front surface and edge defect data. Since the impact of edge defects on front surface yield has yet to be fully determined, Vedula said that K-T and its customers are working on ways to quantify and correlate the edge data to wafer surface yields. The goal is to perfect a comprehensive edge-die yield management solution, with 100% wafer coverage.
Most current work centers on use-case development, Vedula noted, such as figuring out how to put the systems into the production flow and whether the new edge information might suggest adding a cleaning or metrology step, for example. Another in-demand use-case is to become a defect library generator in the fabs, building up the statistical databases, identifying critical DOIs, and prioritizing layers with high levels of edge-defect density. This ability to disposition or "bin" edge defects into the proper categories will be a big help to the IC manufacturers.
Two tools are running through their beta-site paces, one in a North American fab, the other in a European facility. Vedula said shipments are expected to begin in 4Q06 or 1Q07. (For more information on the new K-T system, check out the video.)
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