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Don't be surprised by news that Intel's EUV litho efforts are lagging |
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Nov 17, 2006 at 12:13 PM |
A headline in yesterday's EETimes online edition hit the nail on the head: "EUV making slow progress, says Intel." Mark LaPedus's story quotes Intel's Mike Mayberry, who says, "There's not a whole lot different with [EUV technology] from a year ago." The VP adds, "When we go to 32 nm, we will have some immersion lithography."
Color me not surprised.
Despite assurances to the contrary, it's been clear to many of us tracking litho technology that EUV would not be ready in time for Intel's---or anyone else's---32-nm process node in 2009. As Mark notes in his story, the Intel folks started wavering in February (around the time of the annual SPIE litho lovefest), but the signs of trouble with Intel's efforts to make EUVL a production-worthy approach had been evident before that. EUV's top three sticking points---adequately powerful light sources, dependable photoresists, and defect-free photomasks--have not become that much less sticky than they were a year or so ago. Yes, the first EUVL systems have shipped, but those are demo tools, not production units.
That the big-dog chipmaker will now join the immersion litho parade is a bit newer news, since the company line had been more about sticking with "dry" high-NA ArF, at least through the 45-nm node, than adopting the emerging "wet" approach. I'd be curious to know if Intel has any 45-nm IML tools on order, since the company needs to play catchup in order to master the wet stuff. Even if it does, Intel will have to wait its turn, because of apparent production bottlenecks at the scanner manufacturers' factories.
If anyone has any enlightening information or opinions on the fate of EUVL and/or Intel's lithography roadmap and strategies, please share your comments with Chip Shots or directly with me.
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| Senior Technical Program Manager (Dublin, Ireland, 02/04/2008) | | Embedded Support Engineer (Intel Shannon, Co Clare, Ireland, 19/03/2008) | | Senior Component Design Engineer (Intel Shannon, Co Clare, Ireland, 19/03/2008) | | Senior Process Development Photolithography Engineer (Portland, 22/11/2007) | | Application Developer Engineering Manager (Silicon Valley , 14/09/2007) |
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