The worlds of information technology, nanotechnology, and biotechnology will soon converge in "fusion technology," predicts C.G.
Hwang. Speaking at this morning's IEDM plenary session here in San Francisco, the Samsung executive's address, generically titled "New Paradigms in the Silicon Industry," offered a stimulating view of where the chip industry has been and where it is going...with a distinctly Samsungian flavor.
Drawing on his experiences as a business traveler to demonstrate the blistering pace of silicon-based technology, the much-lauded Hwang (the same gent who added SEMI's Akira Inoue EHS award to his wall of fame last week) showed how the memory capacities of the phones, MP3 players, digicams, and other devices he carries on the road have grown from about 1 Gb in 2002 to 60 Gb in 2006. He pointed out that memory density has doubled each year since 1999, in a sense outrunning Moore's Law. He then mentioned a NAND made by Samsung, which would be the first of many examples of correlating industry trends with recent technological advances from his company.
In his outlook for semi technology, he believes that silicon technology can be extended to 10 nm, with the help of 3-D structures and other CMOS enhancers. Beyond CMOS, approaches such as quantum and molecular electronics may come into play. He then went through several "evolution of" presentations, starting with DRAM, followed by NAND flash and logic.
As for DRAM, he said that recess cell array transistor (RCAT) can be extended down to 50 nm, with FinFET structures taking hold in the 50 to 30 nm range and some sort of vertical transistor necessary below 30 nm. The trend toward an ever-more-compact cell size, coupled with better cost effectiveness, continues to be the main driver in the traditional memory world.
As for DRAM's rapidly evolving NAND flash cousin, he showed a slide of the company's latest, greatest 45-nm, 32-Gb DRAM, which he said is the first to employ a charge trap flash (CTF) approach and should go into mass production in 2008. While floating gates will carry the day until about 50 nm, he described how CTF uses no floating gates and can reduce cell height by 80%, resulting in a big decrease in the number of process steps.
With logic gate lengths of 30 nm already in the fabs, Hwang posits gates of 5-7 nm by 2020. He believes the rate of shrinks will slow by 2010 or so, with strained silicon pushing to 45 nm, a high-k dielectric/metal gate solution taking over down to 32 nm, and some sort of 3-D transistor needed for 22 nm. As for interconnect, lower and lower k dielectrics will work until 22 nm, when he sees the need for an air-gap insulating layer. In another Samsung moment, he showed a device set for production in late 2007 that uses stress proximity technology, dual-stress liners, and ultra-low-k materials to achieve a 30% performance pop and 20% speed boost.
After discussing a twin silicon nanowire FET, "with gates all around," he returned to one of his key themes: 3-D technology. He said 3-D "will overcome the scaling limitation of silicon technology and keep doubling density, while maintaining low cost." He showed a multistacked cell used in a CTF-based NAND device, then went on to relate other chip stacking technologies, including a "through silicon via" technique developed by---you guessed it---Samsung, the first of its kind that does the stacking without wiring. "In the future, packaging will not be simply back-end technology," he emphasized, "but will be a core technology in maximizing silicon technology."
Returning to his theme of "fusion technology," he detailed the OneNAND memory chip, which combines a NAND core, with SRAM, logic, and NOR interface elements. He said it has shown read speeds 4X that of normal NAND and write speeds 46X of today's flash devices, thanks to the speed maximization provided by the SRAM. He also debuted Samsung's OneDRAM chip, the company's second fusion memory product, which he said runs 3-D graphics five times faster than the current devices.
The true "fusionization of technology," according to Hwang, will come when logic and memory are combined with stacks of image sensors, MEMS, and other devices, and eventually integrated with implantables and other biomedical micro- and nanosystems. The ultimate goal, he believes, is for the semiconductor to match the human brain in memory and processing power. Logic can already match the processing speed, but memory density does not yet come close to the brain's capacity. He did predict though that around 2020, a "pseudo human brain" will be available. (I hope the prototypes will be ready in time for my own brain replacement procedure.)
He closed with a favorite aphorism: "The future is not to be predicted, it is to be created." Certainly Samsung seems to be in creation mode when it comes to its corporate future and its ongoing quest for domination of the global electronics marketplace.
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