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Post-IEDM musings: One "missed" paper mines FEOL surface vein |
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Dec 19, 2006 at 12:45 PM |
As noted during my attempts to siphon out some meaning from the IEDM deluge last week, it was impossible to check out more than a healthy smattering of papers when the conference was in full flood mode or even when it finally, mercifully, trickled to an end.
Unless, of course, you're one of those people with no life, who think that reading the voluminous proceedings in its entirety is great fun. (If you are one of those people, you should seek help. Now.)
That being said, I have scanned over several sessions' worth of papers that I was unable (or unwilling) to hear first hand. Hidden among the treasure trove of high-end device engineering and emerging technology R&D was a Sematech team's presentation that offers a possible solution for a problematic advanced front-end-of-line surface treatment application, a topic much in the Chip Shots mix of late.
B.S. Ju and the rest of the authors claim to have developed "a new dry etch process that removes high-k films from the source/drain region with plasma treatment after gate patterning." The novel in situ process "shows complete removal of the high-k without undercutting/footing or substrate recess." The post-high-k dry etch treatment effectively "heals" the etch damage, which significantly decreases gate edge leakage current. "The significantly lower leakage current from the STI-edge capacitor compared to the source/drain edge device indicates that the defects induced at the gate edge [are] effectively passivated by the in situ O2 treatment," the report concludes.
As usual, I need to ask the Big Question: Can this process enhancement meet the test of manufacturability? The data do look very sound, but until the technique finds its legs in a fab line, is successfully integrated into the flow, and helps ramp those metal/high-k-gate-stacked chips to acceptable yield levels, it will remain a nice piece of research work.
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