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Final post-IEDM musings: Road to 32 nm looks pretty good...for now |
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Dec 20, 2006 at 10:00 AM |
Before moving on to other topics, here are some final post-IEDM musings and observations on several themes and issues that emerged from this year's conference (and related events such as the Applied Materials panel).
Although BEOL/interconnect issues will be a bit bumpy on the road to 32 nm, the front -end/transistor-formation process development continues to be the most challenging.
Perhaps the most overriding theme in this year's IEDM was power and power management, with no easy answers seen for leakage, heat dissipation, and the like. Most prognosticators see the transistor remaining planar for the time being, but FinFETs and other vertical architectures are coming on strong, and a few 32-nm devices might grow fins. Tungsten contact barriers will hit the yield and reliability wall at 45 nm, so copper or another barrier material will have to be perfected for the stack at 32 nm.
Strain engineering still has plenty of gas left in its tank to drive down the roadmap to at least 32 nm. High-k/metal gates have taken great strides toward manufacturability on the nMOS side, but pMOS remains problematic. Hyper-NA immersion lithography has successfully entered early volume production, with defect densities seen to be close to those of dry litho. IML looks likely to push down to at least 32 nm as well, as long as the refractive combination of liquid and lens can be tweaked and the resists improved. In the interconnect realm, true ultra-low-k dielectric materials (down to 2.4 k) have finally been introduced and devices with 11 or 12 copper-metal layers reside in the advanced logic fabs.
There will be more heterogeneous device types, with logic, DRAM, and flash needing ever-more-divergent architectural and process solutions and an even-broader palette of specifically tuned enabling materials. Another point of divergence is power, with low- and high-voltage chips becoming less, not more, similar. Chipsets that integrate analog, digital, RF, and even MEMS onto a CMOS platform face compatibility, complexity, and cost issues as designers attempt to cram more functionality onto the silicon.
The affordability of new, exotic materials development is questionable, when the likely market may be only a few hundreds of millions of dollars or even a few tens of millions and the chances for a decent return on investment for the materials developers are slim to none. Another point of concern is the viability of design for manufacturability strategies, considering the increasingly eclectic nature of these devices and their inherent process variabilities.
Although experts such as those on the AMAT panel believe that, despite formidable engineering and cost challenges, 32 nm will happen on time, it will also be a transitional process generation for logic, flash, and DRAM, with many fundamental changes necessary to advance to 22 nm and beyond. Next year's IEDM may offer some early glimpses of which directions the industry might take as it arrives at the 32-nm crossroads.
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