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SPIE Litho nuggets: TI's Stork doesn't deviate from variability message |
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Feb 26, 2007 at 05:06 PM |
Several times over the past year or so, at multiple venues, I've heard Texas Instruments' Hans Stork hammer home the increasing importance of process variations as the chipmaking industry hurtles down the half-pitch highway.
During his plenary presentation at this year's edition of SPIE's Advanced Lithography event, the TI CTO/SVP again staked his claim to the title of Grand Vizier of Variability.
In his introduction, he noted that the "issue of variations is intrinsically linked to nanoscale CMOS patterning and imaging." Variabilities can range from the fab-to-fab and lot-to-lot variety all the way down beyond wafer-to-wafer to the die-to-die and cell-to-cell levels. They can be systematic, stochastic, and time dependent, he said. Even immediately adjacent die, once residing in a comfort zone of control and predictability, can be quite variable from one another.
"Variability...it's figuring out the one in a million or more that doesn't work," quipped Stork. Noting the thorny issue of BEOL-related delays, where 50% of delays in typical dense logic are caused by interconnect resistivity and the like---and the balancing act of twisting transistor-strain and other FEOL knobs ever further---the Vizier pronounced that "we're in a pretty tight box to break through both performance gain and destiny gain at the same time."
When it comes to the assessing the effects of process variations, Stork stressed that the focus needs to be within the die itself, on the local environment, rather than on the global level. Such local effects can be---and must be---predicted, so the margin of error can be reduced where possible. Many simulations don't take local variations into account. In other words, local variations (die level) must be treated differently than global variations (wafer level).
In touching on the handoff from design to manufacturing, Stork said that "only when the physical characteristics are identical, will we have transistors that perform identically," adding later that "design rules are effective when they're few of them, and they're very clear....We have to strike a balance between doing things model based and doing things rule based."
When conference chairman Chris Progler opened the floor to questions, litho guru Chris Mack piped up with a zinger for the Vizier: "Are the challenges of scaling CMOS harder or easier after you lay off your R&D team?"
Mack's query alludes to the recent decision at TI to close the Kilby Fab and to hand over much of its 32-nm and beyond process development to its foundry partners---a move that shocked much of the chipmaking community and still has many scratching their heads (including this reporter).
Stork obviously couldn't deflect the good-natured Mack Attack as directly as some in the standing-room-only audience would have liked. In the process of answering the question, the Vizier's words took on a certain, um, variability.
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